JP2012186296A5 - - Google Patents

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Publication number
JP2012186296A5
JP2012186296A5 JP2011048021A JP2011048021A JP2012186296A5 JP 2012186296 A5 JP2012186296 A5 JP 2012186296A5 JP 2011048021 A JP2011048021 A JP 2011048021A JP 2011048021 A JP2011048021 A JP 2011048021A JP 2012186296 A5 JP2012186296 A5 JP 2012186296A5
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JP
Japan
Prior art keywords
layer
pad
wiring board
metal layer
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011048021A
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English (en)
Japanese (ja)
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JP5675443B2 (ja
JP2012186296A (ja
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Priority to JP2011048021A priority Critical patent/JP5675443B2/ja
Priority claimed from JP2011048021A external-priority patent/JP5675443B2/ja
Priority to US13/410,031 priority patent/US9236334B2/en
Publication of JP2012186296A publication Critical patent/JP2012186296A/ja
Publication of JP2012186296A5 publication Critical patent/JP2012186296A5/ja
Application granted granted Critical
Publication of JP5675443B2 publication Critical patent/JP5675443B2/ja
Active legal-status Critical Current
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JP2011048021A 2011-03-04 2011-03-04 配線基板及び配線基板の製造方法 Active JP5675443B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011048021A JP5675443B2 (ja) 2011-03-04 2011-03-04 配線基板及び配線基板の製造方法
US13/410,031 US9236334B2 (en) 2011-03-04 2012-03-01 Wiring substrate and method for manufacturing wiring substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011048021A JP5675443B2 (ja) 2011-03-04 2011-03-04 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2012186296A JP2012186296A (ja) 2012-09-27
JP2012186296A5 true JP2012186296A5 (enExample) 2014-01-09
JP5675443B2 JP5675443B2 (ja) 2015-02-25

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Family Applications (1)

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JP2011048021A Active JP5675443B2 (ja) 2011-03-04 2011-03-04 配線基板及び配線基板の製造方法

Country Status (2)

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US (1) US9236334B2 (enExample)
JP (1) JP5675443B2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117825B2 (en) 2012-12-06 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate pad structure
TWI487444B (zh) * 2013-05-07 2015-06-01 Unimicron Technology Corp 承載基板及其製作方法
US9491871B2 (en) 2013-05-07 2016-11-08 Unimicron Technology Corp. Carrier substrate
CN104168706B (zh) * 2013-05-17 2017-05-24 欣兴电子股份有限公司 承载基板及其制作方法
JP6266907B2 (ja) * 2013-07-03 2018-01-24 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP6161437B2 (ja) * 2013-07-03 2017-07-12 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP6131135B2 (ja) * 2013-07-11 2017-05-17 新光電気工業株式会社 配線基板及びその製造方法
JP6223909B2 (ja) * 2013-07-11 2017-11-01 新光電気工業株式会社 配線基板及びその製造方法
KR20150040577A (ko) * 2013-10-07 2015-04-15 삼성전기주식회사 패키지 기판
TWI550801B (zh) * 2013-11-13 2016-09-21 南茂科技股份有限公司 封裝結構及其製造方法
US20160233188A1 (en) * 2013-12-02 2016-08-11 Smartrac Technology Gmbh Contact bumps methods of making contact bumps
KR20150064976A (ko) * 2013-12-04 2015-06-12 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US10020275B2 (en) * 2013-12-26 2018-07-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductive packaging device and manufacturing method thereof
US20150195912A1 (en) 2014-01-08 2015-07-09 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Substrates With Ultra Fine Pitch Flip Chip Bumps
JP6133227B2 (ja) * 2014-03-27 2017-05-24 新光電気工業株式会社 配線基板及びその製造方法
KR102211741B1 (ko) * 2014-07-21 2021-02-03 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP5795415B1 (ja) * 2014-08-29 2015-10-14 新光電気工業株式会社 配線基板及びその製造方法
JP6626687B2 (ja) * 2015-10-28 2019-12-25 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2017084997A (ja) * 2015-10-29 2017-05-18 イビデン株式会社 プリント配線板及びその製造方法
JP6619294B2 (ja) * 2016-05-24 2019-12-11 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
JP6594264B2 (ja) * 2016-06-07 2019-10-23 新光電気工業株式会社 配線基板及び半導体装置、並びにそれらの製造方法
TWI712344B (zh) * 2017-08-18 2020-12-01 景碩科技股份有限公司 可做電性測試的多層電路板及其製法
TWI719241B (zh) * 2017-08-18 2021-02-21 景碩科技股份有限公司 可做電性測試的多層電路板及其製法
KR102531762B1 (ko) 2017-09-29 2023-05-12 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
US10347507B2 (en) * 2017-09-29 2019-07-09 Lg Innotek Co., Ltd. Printed circuit board
WO2019066977A1 (en) * 2017-09-29 2019-04-04 Intel Corporation FIRST-LEVEL THIN-LEVEL INTERCONNECTIONS DEFINED BY AUTOCATALYTIC METAL FOR LITHOGRAPHIC INTERCONNECTION HOLES
KR102551747B1 (ko) 2018-09-13 2023-07-06 삼성전자주식회사 반도체 패키지
CN110783728A (zh) * 2018-11-09 2020-02-11 广州方邦电子股份有限公司 一种柔性连接器及制作方法
JP2020188209A (ja) * 2019-05-16 2020-11-19 イビデン株式会社 プリント配線板とプリント配線板の製造方法
US10950531B2 (en) * 2019-05-30 2021-03-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US20210111110A1 (en) * 2019-10-09 2021-04-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP2021132068A (ja) * 2020-02-18 2021-09-09 イビデン株式会社 プリント配線板、プリント配線板の製造方法
US12191161B2 (en) * 2020-12-23 2025-01-07 Intel Corporation Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors
CN116528466A (zh) * 2022-01-21 2023-08-01 奥特斯奥地利科技与系统技术有限公司 具有突出部的部件承载件和制造方法
KR20230140717A (ko) * 2022-03-30 2023-10-10 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지
CN116895636B (zh) * 2023-09-11 2024-01-12 芯爱科技(南京)有限公司 封装基板及其制法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010768A (en) * 1995-11-10 2000-01-04 Ibiden Co., Ltd. Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler
DE69936235T2 (de) * 1998-02-26 2007-09-13 Ibiden Co., Ltd., Ogaki Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern
DE19907168C1 (de) * 1999-02-19 2000-08-10 Micronas Intermetall Gmbh Schichtanordnung sowie Verfahren zu deren Herstellung
JP3635219B2 (ja) 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
US6457234B1 (en) * 1999-05-14 2002-10-01 International Business Machines Corporation Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond
JP2001217523A (ja) * 2000-02-01 2001-08-10 Rohm Co Ltd チップ型半導体装置の実装構造
US7838779B2 (en) 2005-06-17 2010-11-23 Nec Corporation Wiring board, method for manufacturing same, and semiconductor package
JP4890959B2 (ja) * 2005-06-17 2012-03-07 日本電気株式会社 配線基板及びその製造方法並びに半導体パッケージ
JP2008004687A (ja) * 2006-06-21 2008-01-10 Shinko Electric Ind Co Ltd 半導体装置の製造方法
TWI319615B (en) * 2006-08-16 2010-01-11 Phoenix Prec Technology Corp Package substrate and manufacturing method thereof
US7595553B2 (en) * 2006-11-08 2009-09-29 Sanyo Electric Co., Ltd. Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus
TWI331494B (en) * 2007-03-07 2010-10-01 Unimicron Technology Corp Circuit board structure
JP4800253B2 (ja) * 2007-04-04 2011-10-26 新光電気工業株式会社 配線基板の製造方法
JP2008258520A (ja) * 2007-04-09 2008-10-23 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板

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