JP2009182118A5 - - Google Patents

Download PDF

Info

Publication number
JP2009182118A5
JP2009182118A5 JP2008019261A JP2008019261A JP2009182118A5 JP 2009182118 A5 JP2009182118 A5 JP 2009182118A5 JP 2008019261 A JP2008019261 A JP 2008019261A JP 2008019261 A JP2008019261 A JP 2008019261A JP 2009182118 A5 JP2009182118 A5 JP 2009182118A5
Authority
JP
Japan
Prior art keywords
layer
forming
wiring
metal layer
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008019261A
Other languages
English (en)
Japanese (ja)
Other versions
JP5113544B2 (ja
JP2009182118A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2008019261A priority Critical patent/JP5113544B2/ja
Priority claimed from JP2008019261A external-priority patent/JP5113544B2/ja
Priority to US12/324,916 priority patent/US8066862B2/en
Publication of JP2009182118A publication Critical patent/JP2009182118A/ja
Publication of JP2009182118A5 publication Critical patent/JP2009182118A5/ja
Application granted granted Critical
Publication of JP5113544B2 publication Critical patent/JP5113544B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008019261A 2008-01-30 2008-01-30 配線基板の製造方法 Expired - Fee Related JP5113544B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008019261A JP5113544B2 (ja) 2008-01-30 2008-01-30 配線基板の製造方法
US12/324,916 US8066862B2 (en) 2008-01-30 2008-11-28 Manufacturing method of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008019261A JP5113544B2 (ja) 2008-01-30 2008-01-30 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009182118A JP2009182118A (ja) 2009-08-13
JP2009182118A5 true JP2009182118A5 (enExample) 2011-01-13
JP5113544B2 JP5113544B2 (ja) 2013-01-09

Family

ID=40898113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008019261A Expired - Fee Related JP5113544B2 (ja) 2008-01-30 2008-01-30 配線基板の製造方法

Country Status (2)

Country Link
US (1) US8066862B2 (enExample)
JP (1) JP5113544B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5436995B2 (ja) * 2009-09-14 2014-03-05 新光電気工業株式会社 配線基板及びその製造方法
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
CN103717010A (zh) * 2012-10-08 2014-04-09 苏州卓融水处理科技有限公司 一种增强无核封装基板种子层附着力的处理方法
TWI528517B (zh) * 2013-03-26 2016-04-01 威盛電子股份有限公司 線路基板、半導體封裝結構及線路基板製程
JP2016076533A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 バンプ付きプリント配線板およびその製造方法
JP2017152536A (ja) * 2016-02-24 2017-08-31 イビデン株式会社 プリント配線板及びその製造方法
KR20220028310A (ko) * 2020-08-28 2022-03-08 삼성전자주식회사 배선 구조체, 이의 제조 방법 및 배선 구조체를 포함하는 반도체 패키지
WO2022191180A1 (ja) * 2021-03-10 2022-09-15 凸版印刷株式会社 多層配線基板
EP4319510A4 (en) * 2021-03-22 2024-10-02 Panasonic Intellectual Property Management Co., Ltd. WIRING BODY, MOUNTING SUBSTRATE, WIRING TRANSFER BOARD WITH WIRING, INTERMEDIATE MATERIAL FOR WIRING BODY, AND METHOD FOR MANUFACTURING WIRING BODY
JP7721953B2 (ja) * 2021-04-28 2025-08-13 Ｔｏｐｐａｎホールディングス株式会社 多層配線基板
JP2022170153A (ja) * 2021-04-28 2022-11-10 凸版印刷株式会社 多層配線基板
KR20230044059A (ko) * 2021-09-24 2023-04-03 삼성전자주식회사 반도체 패키지
JP2023119425A (ja) * 2022-02-16 2023-08-28 イビデン株式会社 配線基板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4282777B2 (ja) 1996-10-16 2009-06-24 株式会社トッパンＮｅｃサーキットソリューションズ 半導体装置用基板及び半導体装置の製造方法
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
JP4356215B2 (ja) * 1999-11-10 2009-11-04 凸版印刷株式会社 フレクシャ及びその製造方法ならびにそれに用いるフレクシャ用基板
JP2002314228A (ja) * 2001-04-19 2002-10-25 Toppan Printing Co Ltd 配線回路基板およびその製造方法
US6815709B2 (en) * 2001-05-23 2004-11-09 International Business Machines Corporation Structure having flush circuitry features and method of making
JPWO2003032701A1 (ja) * 2001-09-28 2005-01-27 富士通株式会社 多層配線基板の製造方法およびこれにより製造される多層配線基板
JP2003218516A (ja) * 2002-01-23 2003-07-31 Shinko Electric Ind Co Ltd 配線基板の製造方法
CN1291069C (zh) * 2003-05-31 2006-12-20 香港科技大学 微细间距倒装焊凸点电镀制备方法
TWI251920B (en) * 2003-10-17 2006-03-21 Phoenix Prec Technology Corp Circuit barrier structure of semiconductor package substrate and method for fabricating the same
JP2006049804A (ja) * 2004-07-07 2006-02-16 Shinko Electric Ind Co Ltd 配線基板の製造方法
US20060022304A1 (en) * 2004-07-29 2006-02-02 Rohm And Haas Electronic Materials Llc Dielectric structure
TWI261329B (en) * 2005-03-09 2006-09-01 Phoenix Prec Technology Corp Conductive bump structure of circuit board and method for fabricating the same
US20070158199A1 (en) * 2005-12-30 2007-07-12 Haight Scott M Method to modulate the surface roughness of a plated deposit and create fine-grained flat bumps

Similar Documents

Publication Publication Date Title
JP2009182118A5 (enExample)
JP2012028735A5 (enExample)
JP2015070007A5 (enExample)
JP2012094734A5 (enExample)
JP2009283739A5 (enExample)
JP2008300782A5 (enExample)
JP2012186296A5 (enExample)
JP2012019080A5 (enExample)
JP2007520081A5 (enExample)
JP2010519738A5 (enExample)
JP2010067887A5 (enExample)
JP2014239186A5 (enExample)
JP2012248703A5 (enExample)
JP2014103295A5 (enExample)
JP2009105311A5 (enExample)
JP2015159197A5 (enExample)
WO2008105372A1 (ja) 磁気記憶装置の製造方法および磁気記憶装置
JP2011061116A5 (enExample)
JP2014067941A5 (enExample)
JP2009260216A5 (enExample)
JP2015211077A5 (enExample)
KR20160012857A (ko) 필러 구조를 가진 기판 및 그 제조 방법
JP2013084852A5 (enExample)
TW201230901A (en) Printed circuit board and method for manufacturing the same
EP2019573A3 (en) Wired circuit board and producing method thereof