JP2015211077A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2015211077A5 JP2015211077A5 JP2014090406A JP2014090406A JP2015211077A5 JP 2015211077 A5 JP2015211077 A5 JP 2015211077A5 JP 2014090406 A JP2014090406 A JP 2014090406A JP 2014090406 A JP2014090406 A JP 2014090406A JP 2015211077 A5 JP2015211077 A5 JP 2015211077A5
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- hole
- layer
- forming
- substrate body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014090406A JP6251629B2 (ja) | 2014-04-24 | 2014-04-24 | 配線基板及び配線基板の製造方法 |
| US14/687,126 US9318351B2 (en) | 2014-04-24 | 2015-04-15 | Wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014090406A JP6251629B2 (ja) | 2014-04-24 | 2014-04-24 | 配線基板及び配線基板の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015211077A JP2015211077A (ja) | 2015-11-24 |
| JP2015211077A5 true JP2015211077A5 (enExample) | 2017-02-16 |
| JP6251629B2 JP6251629B2 (ja) | 2017-12-20 |
Family
ID=54335479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014090406A Active JP6251629B2 (ja) | 2014-04-24 | 2014-04-24 | 配線基板及び配線基板の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9318351B2 (enExample) |
| JP (1) | JP6251629B2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3216050B1 (en) | 2014-11-05 | 2021-09-08 | Corning Incorporated | Bottom-up electrolytic via plating method |
| US9666507B2 (en) * | 2014-11-30 | 2017-05-30 | United Microelectronics Corp. | Through-substrate structure and method for fabricating the same |
| JP7307898B2 (ja) * | 2017-03-24 | 2023-07-13 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
| US10917966B2 (en) * | 2018-01-29 | 2021-02-09 | Corning Incorporated | Articles including metallized vias |
| US20190357364A1 (en) * | 2018-05-17 | 2019-11-21 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component Carrier With Only Partially Filled Thermal Through-Hole |
| WO2020138221A1 (ja) * | 2018-12-26 | 2020-07-02 | 京セラ株式会社 | 配線基板、電子装置及び電子モジュール |
| CN113711347A (zh) * | 2019-04-15 | 2021-11-26 | 大日本印刷株式会社 | 贯通电极基板、电子单元、贯通电极基板的制造方法以及电子单元的制造方法 |
| JP2022147360A (ja) * | 2021-03-23 | 2022-10-06 | 凸版印刷株式会社 | 多層配線基板およびその製造方法 |
| JP7746684B2 (ja) * | 2021-05-11 | 2025-10-01 | 大日本印刷株式会社 | 貫通電極基板 |
| WO2025047765A1 (ja) * | 2023-08-30 | 2025-03-06 | 京セラ株式会社 | 印刷配線板及びビルドアップ印刷配線板 |
| CN120015732B (zh) * | 2025-02-14 | 2025-11-14 | 无锡缶英微电子科技有限公司 | 一种硅电容器 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3810659B2 (ja) * | 2001-08-28 | 2006-08-16 | 日本メクトロン株式会社 | ヴィアホールの充填方法 |
| US6853046B2 (en) * | 2002-09-24 | 2005-02-08 | Hamamatsu Photonics, K.K. | Photodiode array and method of making the same |
| JP4098673B2 (ja) | 2003-06-19 | 2008-06-11 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
| JP2007005404A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
| JP4552770B2 (ja) * | 2005-06-21 | 2010-09-29 | パナソニック電工株式会社 | 半導体基板への貫通配線の形成方法 |
| US8330256B2 (en) * | 2008-11-18 | 2012-12-11 | Seiko Epson Corporation | Semiconductor device having through electrodes, a manufacturing method thereof, and an electronic apparatus |
| JP2013077807A (ja) * | 2011-09-13 | 2013-04-25 | Hoya Corp | 基板製造方法および配線基板の製造方法 |
-
2014
- 2014-04-24 JP JP2014090406A patent/JP6251629B2/ja active Active
-
2015
- 2015-04-15 US US14/687,126 patent/US9318351B2/en active Active