JP6251629B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

Info

Publication number
JP6251629B2
JP6251629B2 JP2014090406A JP2014090406A JP6251629B2 JP 6251629 B2 JP6251629 B2 JP 6251629B2 JP 2014090406 A JP2014090406 A JP 2014090406A JP 2014090406 A JP2014090406 A JP 2014090406A JP 6251629 B2 JP6251629 B2 JP 6251629B2
Authority
JP
Japan
Prior art keywords
metal layer
layer
hole
substrate body
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014090406A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015211077A (ja
JP2015211077A5 (enExample
Inventor
昌宏 春原
昌宏 春原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2014090406A priority Critical patent/JP6251629B2/ja
Priority to US14/687,126 priority patent/US9318351B2/en
Publication of JP2015211077A publication Critical patent/JP2015211077A/ja
Publication of JP2015211077A5 publication Critical patent/JP2015211077A5/ja
Application granted granted Critical
Publication of JP6251629B2 publication Critical patent/JP6251629B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2014090406A 2014-04-24 2014-04-24 配線基板及び配線基板の製造方法 Active JP6251629B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014090406A JP6251629B2 (ja) 2014-04-24 2014-04-24 配線基板及び配線基板の製造方法
US14/687,126 US9318351B2 (en) 2014-04-24 2015-04-15 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014090406A JP6251629B2 (ja) 2014-04-24 2014-04-24 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2015211077A JP2015211077A (ja) 2015-11-24
JP2015211077A5 JP2015211077A5 (enExample) 2017-02-16
JP6251629B2 true JP6251629B2 (ja) 2017-12-20

Family

ID=54335479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014090406A Active JP6251629B2 (ja) 2014-04-24 2014-04-24 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9318351B2 (enExample)
JP (1) JP6251629B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI689630B (zh) 2014-11-05 2020-04-01 美商康寧公司 底部向上電解質通孔鍍覆方法
US9666507B2 (en) * 2014-11-30 2017-05-30 United Microelectronics Corp. Through-substrate structure and method for fabricating the same
JP7307898B2 (ja) * 2017-03-24 2023-07-13 大日本印刷株式会社 貫通電極基板及びその製造方法
US10917966B2 (en) * 2018-01-29 2021-02-09 Corning Incorporated Articles including metallized vias
US20190357364A1 (en) * 2018-05-17 2019-11-21 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With Only Partially Filled Thermal Through-Hole
JP7191982B2 (ja) * 2018-12-26 2022-12-19 京セラ株式会社 配線基板、電子装置及び電子モジュール
KR102615059B1 (ko) * 2019-04-15 2023-12-19 다이니폰 인사츠 가부시키가이샤 관통 전극 기판, 전자 유닛, 관통 전극 기판의 제조 방법 및 전자 유닛의 제조 방법
JP2022147360A (ja) * 2021-03-23 2022-10-06 凸版印刷株式会社 多層配線基板およびその製造方法
JP7746684B2 (ja) * 2021-05-11 2025-10-01 大日本印刷株式会社 貫通電極基板
WO2025047765A1 (ja) * 2023-08-30 2025-03-06 京セラ株式会社 印刷配線板及びビルドアップ印刷配線板
CN120015732B (zh) * 2025-02-14 2025-11-14 无锡缶英微电子科技有限公司 一种硅电容器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3810659B2 (ja) * 2001-08-28 2006-08-16 日本メクトロン株式会社 ヴィアホールの充填方法
US6853046B2 (en) * 2002-09-24 2005-02-08 Hamamatsu Photonics, K.K. Photodiode array and method of making the same
JP4098673B2 (ja) 2003-06-19 2008-06-11 新光電気工業株式会社 半導体パッケージの製造方法
JP2007005404A (ja) * 2005-06-21 2007-01-11 Matsushita Electric Works Ltd 半導体基板への貫通配線の形成方法
JP4552770B2 (ja) * 2005-06-21 2010-09-29 パナソニック電工株式会社 半導体基板への貫通配線の形成方法
US8330256B2 (en) * 2008-11-18 2012-12-11 Seiko Epson Corporation Semiconductor device having through electrodes, a manufacturing method thereof, and an electronic apparatus
JP2013077807A (ja) * 2011-09-13 2013-04-25 Hoya Corp 基板製造方法および配線基板の製造方法

Also Published As

Publication number Publication date
US9318351B2 (en) 2016-04-19
US20150311154A1 (en) 2015-10-29
JP2015211077A (ja) 2015-11-24

Similar Documents

Publication Publication Date Title
JP6251629B2 (ja) 配線基板及び配線基板の製造方法
JP6286169B2 (ja) 配線基板及びその製造方法
JP6502464B2 (ja) インダクター及びその製造方法
KR102331611B1 (ko) 전자 부품 장치 및 그 제조 방법
US9247644B2 (en) Wiring board and method for manufacturing the same
US9253897B2 (en) Wiring substrate and method for manufacturing the same
JP5608605B2 (ja) 配線基板の製造方法
JP6594264B2 (ja) 配線基板及び半導体装置、並びにそれらの製造方法
JP2017157666A (ja) 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
JP6341714B2 (ja) 配線基板及びその製造方法
KR20180068203A (ko) 인덕터
JP2011187863A (ja) 配線基板及びその製造方法
JP2019041041A (ja) 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
JP2016048795A (ja) 導体構造要素及び導体構造要素を製造するための方法
JP2014192386A (ja) インターポーザ、及び電子部品パッケージ
JP6532750B2 (ja) 配線基板及びその製造方法
JP2012253227A (ja) 配線基板及びその製造方法
KR102464308B1 (ko) 인덕터
JP4445777B2 (ja) 配線基板、及び配線基板の製造方法
JP2018006450A (ja) 電子部品内蔵基板及びその製造方法と電子部品装置
KR101959864B1 (ko) 리세스 깊이 조절이 가능한 초박형 인쇄회로기판 및 그 제조 방법
JP2017224642A (ja) 配線基板及びその製造方法
US12096556B2 (en) Interconnect substrate and method of making the same
US20240006307A1 (en) Interconnect substrate
US20230422411A1 (en) Substrate structure

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170111

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170111

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20171024

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171101

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171127

R150 Certificate of patent or registration of utility model

Ref document number: 6251629

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150