JP2010004050A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2010004050A JP2010004050A JP2009163904A JP2009163904A JP2010004050A JP 2010004050 A JP2010004050 A JP 2010004050A JP 2009163904 A JP2009163904 A JP 2009163904A JP 2009163904 A JP2009163904 A JP 2009163904A JP 2010004050 A JP2010004050 A JP 2010004050A
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
【解決手段】コア材104の厚みを薄くした構造を採用したビルドアップ型の多層基板108にシリコンチップ102をフリップチップ実装する際に、その多層基板に線膨張係数の小さなコア材を用いた上で、そのコア材の厚みおよび線膨張係数にあわせて、アンダーフィル材112の線膨張係数およびガラス転移点を適切に設計している。
【選択図】図4
Description
前記回路基板に金属バンプを介して半導体素子を接続する工程と、前記半導体素子および前記回路基板の間に封止樹脂組成物を充填する工程と、を含む半導体装置の製造方法であって、前記コア材の厚みは500μm以下であり、前記コア材の室温からガラス転移温度までの面内方向の線膨張係数は15ppm/℃以下であり、前記コア材の室温からガラス転移温度までの厚み方向の線膨張係数は18ppm/℃以下であり、前記封止樹脂組成物の室温からガラス転移温度までの線膨張係数は15ppm/℃以上30ppm/℃以下であり、前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、75≦Tg<112.5T+95の式を満たすことを特徴とする半導体装置の製造方法が提供される。
102 シリコンチップ
104 コア材
106 ビルドアップ層
108 多層基板
110 半田バンプ
112 アンダーフィル材
114 回路配線
120 マザーボード
122 2次ボール
1000 電子デバイス
1−2−1型の多層基板では、コア材の両面に配線層が設けられており、さらにその両側に配線層を有するビルドアップ層が設けられている。すなわち、下側から見て、ビルドアップ層の表面に1層、コア材の両側に2層、ビルドアップ層の表面に1層の配線層が設けられているために1−2−1型の多層基板と称される。
本実施形態においては、インターポーザをはじめとする回路基板への半導体素子の実装方式としては、フリップチップ実装を採用している。図1は、実施の形態に係る半導体パッケージ100を含む電子デバイス1000の構成を説明するための写真である。この半導体パッケージ100では、半導体素子であるシリコンチップ102が、回路基板である多層基板(ラミネート)108上にフリップチップ方式により接続されている。また、シリコンチップ102および多層基板108の間には封止樹脂組成物であるアンダーフィル材112が封入されている。そして、これらの構成要素を含む半導体パッケージ100は、マザーボード120上に接続され、全体として電子デバイス1000を構成している。
図4(a)は、実施の形態に係る半導体パッケージ100の構成を説明するための断面図である。以下に具体的に説明する本実施形態の半導体パッケージ100では、上述の高密度実装の要請を満たすために500μm以下の厚みの薄型多基板(薄型のコア材およびビルドアップ層)108を用いている。
厚さ0.1mmの両面銅張積層板を全面エッチングし、得られた積層板から縦・横方向それぞれ4mm×20mmのテストピースを切り出し、TMA(TAインスツルメント(株)製)を用いて縦・横方向の線膨張係数を5℃/分で測定する(縦方向は圧縮モード、横方向は引っ張りモード)。
銅箔付き絶縁シート2枚の樹脂面を内側にはり合わせ、真空プレスにて圧力2MPa、温度220℃で1時間加熱加圧成形を行い、銅箔を全面エッチングし絶縁樹脂硬化物を得る。得られた絶縁樹脂硬化物から4mm×20mmのテストピースを切り出し、TMA(TAインスツルメント(株)製)を用いて線膨張係数を10℃/分で測定する。なお、ビルドアップ層は面内方向及び厚み方向のCTEが同じであるため、面内方向の引張りモード測定のみを実施すればよい。
まず、樹脂組成物を150℃×120分で硬化後、切削により5×5×10mmの試験片を得る。この試験片をセイコー製TMA/SS120を用いて圧縮荷重5g、−100℃から300℃の温度範囲を昇温速度10℃/分の条件で測定する。このように、TMA式測定装置によりCTEとTgの両方を算出することができる。
また、アンダーフィル材112のTMA法によるガラス転移温度Tg(℃)は、コア材104の厚みをT(mm)とすると、75≦Tgの式を満たし、好ましくは25T+75≦Tgの式を満たし、さらに好ましくは50T+75≦Tgの式を満たす。また、アンダーフィル材112のTMA法によるガラス転移温度Tg(℃)は、Tg<112.5T+95の式を満たし、好ましくは≦100T+95の式を満たし、さらに好ましくは75T+95の式を満たす。アンダーフィル材112のガラス転移温度Tgがこれらの範囲内であれば、温度変化にともなう多層基板108の変形などにより生じる半導体パッケージ100内部の応力を緩和して、温度変化にともなう半導体パッケージ100の損傷を抑制することができる。なお、これらのガラス転移温度Tg(℃)の数値限定は、基本的には、多層基板108の層構造に関係なく成立するものであり、多層基板108のビルドアップ層106の一層あたりの厚みが20〜60μm、銅箔(不図示)の一層あたりの厚みが3〜20μmの範囲にある場合には、特に好適に成立するものである。
(i)シリコンチップ102の回路面にLow−K膜を想定し、ここに加わる応力がLowK材料の層間剥離を進展させないこと
(ii)半田バンプ(ここではSnAgCuを想定)100の予測寿命が温度衝撃試験(−55℃30分、125℃30分)1000サイクル以上であること
(iii)半導体装置の反り変形によるシリコンチップ102の破壊がないこと
(iv)チップシリコンチップ102の側面とアンダーフィル材112界面の剥離応力がアンダーフィルの密着強度以下であること
の4つの観点で応力計算を行い、それぞれの要件を満たすアンダーフィル材の特性を求め、それらを総括した結果、上記のTgの関係式を得るに至った。
2−2−2型の多層基板では、コア材の両面に配線層が設けられており、さらにその両側に配線層を有するビルドアップ層がそれぞれ2層ずつ設けられている。すなわち、下側から見て、2層のビルドアップ層の表面にそれぞれ1層ずつで合計2層、コア材の両側に2層、2層のビルドアップ層の表面にそれぞれ1層ずつで合計2層の配線層が設けられているために2−2−2型の多層基板と称される。
3−2−3型の多層基板では、コア材の両面に配線層が設けられており、さらにその両側に配線層を有するビルドアップ層がそれぞれ3層ずつ設けられている。すなわち、下側から見て、3層のビルドアップ層の表面にそれぞれ1層ずつで合計3層、コア材の両側に2層、3層のビルドアップ層の表面にそれぞれ1層ずつで合計3層の配線層が設けられているために3−2−3型の多層基板と称される。
4−2−4型の多層基板では、コア材の両面に配線層が設けられており、さらにその両側に配線層を有するビルドアップ層がそれぞれ4層ずつ設けられている。すなわち、下側から見て、4層のビルドアップ層の表面にそれぞれ1層ずつで合計4層、コア材の両側に2層、4層のビルドアップ層の表面にそれぞれ1層ずつで合計4層の配線層が設けられているために3−2−3型の多層基板と称される。
なお、実施形態1〜4の半導体装置100の作用効果について理解を容易にするために、従来のFC−BGAの有していた課題について触れつつ、図6に示す従来の薄型FC−BGA型の半導体装置の故障事例を説明するための断面図を用いて説明する。
実施形態1〜4で用いられるコア材104は、上述の厚みおよび線膨張係数の条件を満たし、適切な強度を有していればよく、特に限定するものではないが、例えば、シアネート樹脂とフェノール樹脂とエポキシ樹脂と無機充填材とを含む樹脂組成物を繊維基材(例えばガラス繊維シートなど)に含浸させて硬化させてなる板状の基材(いわゆるプリプレグ)を好適に用いることができる。
上記の樹脂組成物を繊維基材(例えばガラス繊維シートなど)に含浸させて硬化させてなる板状の基材(いわゆるプリプレグ)であるコア材104は、誘電特性、高温多湿下での機械的、電気的接続信頼性等の各種特性に優れたプリント配線板であるインターポーザやマザーボードなどを製造するのに好適である。
以下、実施形態1〜4に用いられるビルドアップ層106を形成する樹脂組成物について説明する。ビルドアップ層106を形成する樹脂組成物は、特に限定されないが、熱硬化性樹脂を含む樹脂組成物で構成されていることが好ましい。これにより、絶縁樹脂層の耐熱性を向上することができる。
次に、多層基板の製造方法について説明する。
図3は、ビルドアップ型インターポーザの設計を説明するための概念図である。実施形態1〜4に用いる積層板である多層基板108は、上述のコア材104を少なくとも1枚、上述のビルドアップ層を少なくとも1枚、さらにそれらの表面に銅箔などからなる回路配線114を少なくとも1枚積層してなるものである。これにより、誘電特性、高温多湿化での機械的、電気的接続信頼性に優れた積層板を得ることができる。
実施形態1〜4で用いられるアンダーフィル材112は、上述の線膨張係数およびガラス転移温度の条件を満たしていればよく、特に限定するものではないが、エポキシ樹脂と、硬化剤と、無機充填材と、シランカップリング剤と、を含むことが好ましい。
X:水素基またはアルキル基
絶縁樹脂層形成用の液状樹脂組成物の原料は以下の通りである。
以下、各成分の配合量は固形分基準である。
シアネート樹脂1を15重量部、シアネート樹脂2を5重量部、エポキシ樹脂を10重量部、フェノール樹脂を10重量部、各々用い、これらを常温でメチルエチルケトンに溶解した。
3.1 絶縁樹脂層付きキャリアA−1の製造
キャリアとして厚み35μm、幅480mmのポリエチレンテレフタレートフィルム(三菱化学ポリエステル社製・ダイヤホイル)を用いた。
繊維布としてガラス織布(ユニチカグラスファイバー社製・「E02Z−SK」、幅360mm、坪量17g/m2)を用いた。
内層回路基板として、絶縁層厚み0.6mm、回路厚み12μm、回路幅及び回路間幅:L/S=50μm/50μmの回路加工が施されたプリント配線板を用いた。
アンダーフィル材の製造で用いた液状樹脂組成物の原料は以下の通りである。
さらに、上記のようにして得られた1−2−1型、2−2−2型、3−2−3型、4−2−4型の多層プリント配線板と、アンダーフィル樹脂UF1〜UF−9と、シリコンチップと、を用いて、表2〜表6に示す組合せによりフリップチップ実装による半導体パッケージを作製した。
図9は、1−2−1型のインターポーザを用いた薄型FC−BGA型の半導体装置でのサーマルサイクル試験の結果を説明するためのグラフである。アンダーフィルの線膨張係数は26ppm/℃で固定した条件で実験を行った。なお、この図の横軸はコア材の厚み(mm)を示し、縦軸はアンダーフィルのTMA法によるガラス転移温度(℃)を示す。後述する図10〜図12についても同様である。
Claims (9)
- コア材の両面にビルドアップ層を積層して多層回路基板を作製する工程と、
前記回路基板に金属バンプを介して半導体素子を接続する工程と、
前記半導体素子および前記回路基板の間に封止樹脂組成物を充填する工程と、を含む半導体装置の製造方法であって、
前記コア材の厚みは500μm以下であり、
前記コア材の室温からガラス転移温度までの面内方向の線膨張係数は15ppm/℃以下であり、
前記コア材の室温からガラス転移温度までの厚み方向の線膨張係数は18ppm/℃以下であり、
前記封止樹脂組成物の室温からガラス転移温度までの線膨張係数は15ppm/℃以上30ppm/℃以下であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、75≦Tg<112.5T+95の式を満たすことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記コア材の厚みは200μm以下であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ビルドアップ層の室温からガラス転移温度までの面内方向の線膨張係数は35ppm/℃以下であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、25T+75≦Tg≦100T+95の式を満たすことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記回路基板の備えるビルドアップ層は7層以上であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、75≦Tg≦75T+95の式を満たすことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記回路基板の備えるビルドアップ層は4層以上6層以下であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、25T+75≦Tg≦100T+95の式を満たすことを特徴とする半導体装置の製造方法。 - コア材の両面にビルドアップ層を積層して多層回路基板を作製する工程と、
前記回路基板に金属バンプを介して半導体素子を接続する工程と、
前記半導体素子および前記回路基板の間に封止樹脂組成物を充填する工程と、を含む半導体装置の製造方法であって、
前記回路基板の備えるビルドアップ層は3層以下であり、
前記コア材の厚みは500μm以下であり、
前記コア材の室温からガラス転移温度までの面内方向の線膨張係数は15ppm/℃以下であり、
前記コア材の室温からガラス転移温度までの厚み方向の線膨張係数は18ppm/℃以下であり、
前記封止樹脂組成物の室温からガラス転移温度までの線膨張係数は15ppm/℃以上30ppm/℃以下であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、50T+75≦Tg<125T+95の式を満たすことを特徴とする半導体装置の製造方法。 - コア材の両面にビルドアップ層を積層して多層回路基板を作製する工程と、
前記回路基板に金属バンプを介して半導体素子を接続する工程と、
前記半導体素子および前記回路基板の間に封止樹脂組成物を充填する工程と、を含む半導体装置の製造方法であって、
前記コア材の厚みは500μm以下であり、
前記コア材はシアネート樹脂とフェノール樹脂とエポキシ樹脂と無機充填材とを含む樹脂組成物を繊維基材に含浸させて硬化させてなり、
前記封止樹脂組成物の室温からガラス転移温度までの線膨張係数は15ppm/℃以上30ppm/℃以下であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、75≦Tg<112.5T+95の式を満たすことを特徴とする半導体装置の製造方法。 - コア材の両面にビルドアップ層を積層して多層回路基板を作製する工程と、
前記回路基板に金属バンプを介して半導体素子を接続する工程と、
前記半導体素子および前記回路基板の間に封止樹脂組成物を充填する工程と、を含む半導体装置の製造方法であって、
前記回路基板の備えるビルドアップ層は3層以下であり、
前記コア材の厚みは500μm以下であり、
前記コア材はシアネート樹脂とフェノール樹脂とエポキシ樹脂と無機充填材とを含む樹脂組成物を繊維基材に含浸させて硬化させてなり、
前記封止樹脂組成物の室温からガラス転移温度までの線膨張係数は15ppm/℃以上30ppm/℃以下であり、
前記封止樹脂組成物のTMA法によるガラス転移温度Tg(℃)は、前記コア材の厚みをT(mm)とすると、50T+75≦Tg<125T+95の式を満たすことを特徴とする半導体装置の製造方法。
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Also Published As
Publication number | Publication date |
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JPWO2008032620A1 (ja) | 2010-01-21 |
KR20110000761A (ko) | 2011-01-05 |
JP4802246B2 (ja) | 2011-10-26 |
CA2630824A1 (en) | 2008-03-20 |
SG160403A1 (en) | 2010-04-29 |
KR20080091086A (ko) | 2008-10-09 |
CN101356643A (zh) | 2009-01-28 |
EP1956648A1 (en) | 2008-08-13 |
TWI374523B (ja) | 2012-10-11 |
KR101195408B1 (ko) | 2012-10-29 |
EP1956648A4 (en) | 2011-09-21 |
WO2008032620A1 (fr) | 2008-03-20 |
US8008767B2 (en) | 2011-08-30 |
CN101356643B (zh) | 2012-04-25 |
CA2630824C (en) | 2013-01-08 |
TW200830486A (en) | 2008-07-16 |
US20090267212A1 (en) | 2009-10-29 |
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