JP2009130196A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2924/151—Die mounting substrate
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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- H05K2201/09—Shape and layout
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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Abstract
【解決手段】第1の電子部品13と、第1の電子部品13が実装される第1の電子部品実装用パッド58,61,62,65を有する第1の配線基板11と、第1の配線基板11の上方に配置された第2の配線基板17と、を備え、第1の電子部品実装用パッド58,61,62,65が第2の配線基板17と対向する側の第1の配線基板11の面に設けられると共に、第1の配線基板11と第2の配線基板17との間に配置された内部接続端子19により、第1の配線基板11と第2の配線基板17とが電気的に接続された半導体装置10であって、第1の電子部品13と対向する部分の第2の配線基板17に第1の電子部品13の一部を収容する凹部94を設けた。
【選択図】図2
Description
図2は、本発明の第1の実施の形態に係る半導体装置の断面図である。
図5は、本発明の第2の実施の形態に係る半導体装置の断面図である。図5において、第1の実施の形態の第2変形例の半導体装置140と同一構成部分には同一符号を付す。
図6は、本発明の第3の実施の形態に係る半導体装置の断面図である。図6において、第1の実施の形態の第2変形例の半導体装置140と同一構成部分には同一符号を付す。
11,151,181 第1の配線基板
12,13,142 第1の電子部品
14 外部接続端子
17,141,152,182,184 第2の配線基板
19 内部接続端子
21 封止樹脂
21A,31B,49A,71B,93A,161B,171B 下面
23,24,182 第2の電子部品
31,71 コア基板
31A,35A,71A,75A,161A,171A 上面
33,73 貫通電極
34,47,56,59,63,67,74,91,103,107,113,202,207,213,217,223 配線
35,49,75,93,161,171 絶縁層
36,51,76,95,163,173 ビア
41〜44,81〜83,87,187,191〜194 配線パターン
45,54,66,97,205,222 内部接続端子用パッド
52 外部接続用パッド
55,57,58,61,62,65,206,211,212,215,216,221 第1の電子部品実装用パッド
72,114,131 貫通部
94,143,153 凹部
85,101,102,105,106,111,112,188,201 第2の電子部品実装用パッド
115 コア部
116 被覆部
225 電子部品収容用貫通部
H1,H2,H3,H4 高さ
Claims (12)
- 第1の電子部品と、前記第1の電子部品が実装される第1の電子部品実装用パッドを有する第1の配線基板と、前記第1の配線基板の上方に配置された第2の配線基板と、を備え、
前記第1の電子部品実装用パッドが前記第2の配線基板と対向する側の前記第1の配線基板の第1の面に設けられると共に、前記第1の配線基板と前記第2の配線基板との間に配置された内部接続端子により、前記第1の配線基板と前記第2の配線基板とが電気的に接続された半導体装置であって、
前記第1の電子部品と対向する部分の前記第2の配線基板に、前記第1の電子部品の一部を収容する凹部を設けたことを特徴とする半導体装置。 - 前記第1の電子部品は、前記第1の配線基板に複数実装されており、
前記凹部は、前記第1の配線基板に実装された複数の前記第1の電子部品のうち、前記第1の配線基板と前記第2の配線基板との間に配置された前記内部接続端子の高さよりも高さの高い前記第1の電子部品と対向する部分の前記第2の配線基板に設けたことを特徴とする請求項1記載の半導体装置。 - 前記第1の配線基板と前記第2の配線基板との間を封止する封止樹脂を設けたことを特徴とする請求項1又は2記載の半導体装置。
- 前記第2の配線基板に、前記凹部の底部に対応する部分の前記第2の配線基板を貫通する貫通部を設けたことを特徴とする請求項1ないし3のうち、いずれか一項記載の半導体装置。
- 前記第2の配線基板は、前記凹部が形成された側とは反対側に位置する前記第2の配線基板の面に第2の電子部品実装用パッドを有し、
前記第2の電子部品実装用パッドに第2の電子部品を実装したことを特徴とする請求項1ないし4のうち、いずれか一項記載の半導体装置。 - 前記内部接続端子は、前記第1の配線基板と前記第2の配線基板との間を所定の間隔に保つためのコア部と、前記コア部を覆う被覆部とを有した導電性ボールであることを特徴とする請求項1ないし5のうち、いずれか一項記載の半導体装置。
- 前記第1の面の反対側に位置する前記第1の配線基板の第2の面に設けられると共に、前記第2の配線基板と電気的に接続される外部接続用パッドを設けたことを特徴とする請求項1ないし6のうち、いずれか一項記載の半導体装置。
- 第1の電子部品と、前記第1の電子部品が実装される第1の電子部品実装用パッドを有する第1の配線基板と、前記第1の配線基板に実装された前記第1の電子部品と対向するように前記第1の配線基板の下方に配置された第2の配線基板と、を備え、
前記第1の配線基板と前記第2の配線基板との間に配置された内部接続端子により、前記第1の配線基板と前記第2の配線基板とが電気的に接続された半導体装置であって、
前記第2の配線基板に、前記第1の電子部品と対向する部分の前記第2の配線基板を貫通すると共に、前記第1の電子部品の一部を収容する電子部品収容用貫通部を設けたことを特徴とする半導体装置。 - 前記第1の電子部品は、複数設けられており、
前記電子部品収容用貫通部は、前記第1の配線基板に実装された複数の前記第1の電子部品のうち、前記第1の配線基板に接続された前記内部接続端子の下端から突出する前記第1の電子部品と対向する部分の前記第2の配線基板に設けたことを特徴とする請求項8記載の半導体装置。 - 前記第1の配線基板と前記第2の配線基板との間を封止する封止樹脂を設けたことを特徴とする請求項8又は9記載の半導体装置。
- 前記第1の配線基板は、前記第1の電子部品実装用パッドが設けられた面の反対側に位置する前記第1の配線基板の面に第2の電子部品実装用パッドを有し、
前記第2の電子部品実装用パッドに第2の電子部品を実装したことを特徴とする請求項8ないし10のうち、いずれか一項記載の半導体装置。 - 前記内部接続端子は、前記第1の配線基板と前記第2の配線基板との間を所定の間隔に保つためのコア部と、前記コア部を覆う被覆部とを有した導電性ボールであることを特徴とする請求項8ないし11のうち、いずれか一項記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007304655A JP5230997B2 (ja) | 2007-11-26 | 2007-11-26 | 半導体装置 |
TW097145456A TWI462250B (zh) | 2007-11-26 | 2008-11-25 | 半導體裝置 |
KR1020080117396A KR101498736B1 (ko) | 2007-11-26 | 2008-11-25 | 반도체 장치 |
US12/277,905 US8208268B2 (en) | 2007-11-26 | 2008-11-25 | Semiconductor apparatus |
CNA2008101784256A CN101447470A (zh) | 2007-11-26 | 2008-11-26 | 半导体装置 |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007304655A JP5230997B2 (ja) | 2007-11-26 | 2007-11-26 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
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JP2009130196A true JP2009130196A (ja) | 2009-06-11 |
JP2009130196A5 JP2009130196A5 (ja) | 2010-11-04 |
JP5230997B2 JP5230997B2 (ja) | 2013-07-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007304655A Active JP5230997B2 (ja) | 2007-11-26 | 2007-11-26 | 半導体装置 |
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US (1) | US8208268B2 (ja) |
JP (1) | JP5230997B2 (ja) |
KR (1) | KR101498736B1 (ja) |
CN (1) | CN101447470A (ja) |
TW (1) | TWI462250B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015525007A (ja) * | 2012-08-15 | 2015-08-27 | アップル インコーポレイテッド | 薄型基板のPoP構造 |
JP2017050310A (ja) * | 2015-08-31 | 2017-03-09 | 新光電気工業株式会社 | 電子部品装置及びその製造方法 |
KR20180065937A (ko) * | 2016-12-07 | 2018-06-18 | 스태츠 칩팩 피티이. 엘티디. | 3d 인터포저 시스템-인-패키지 모듈을 형성하기 위한 반도체 소자 및 방법 |
WO2022209751A1 (ja) * | 2021-03-31 | 2022-10-06 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
US11842991B2 (en) | 2016-12-07 | 2023-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a 3D interposer system-in-package module |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7825514B2 (en) * | 2007-12-11 | 2010-11-02 | Dai Nippon Printing Co., Ltd. | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device |
JP2009182202A (ja) * | 2008-01-31 | 2009-08-13 | Casio Comput Co Ltd | 半導体装置の製造方法 |
JP4930566B2 (ja) * | 2009-10-02 | 2012-05-16 | 富士通株式会社 | 中継基板、プリント基板ユニット、および、中継基板の製造方法 |
US20130181359A1 (en) | 2012-01-13 | 2013-07-18 | TW Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Thinner Package on Package Structures |
US9281292B2 (en) | 2012-06-25 | 2016-03-08 | Intel Corporation | Single layer low cost wafer level packaging for SFF SiP |
CN104347558B (zh) * | 2013-08-05 | 2019-03-15 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
JP6168598B2 (ja) * | 2013-08-21 | 2017-07-26 | 日東電工株式会社 | 光電気混載モジュール |
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Also Published As
Publication number | Publication date |
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TWI462250B (zh) | 2014-11-21 |
KR20090054390A (ko) | 2009-05-29 |
US8208268B2 (en) | 2012-06-26 |
CN101447470A (zh) | 2009-06-03 |
TW200939434A (en) | 2009-09-16 |
US20090135575A1 (en) | 2009-05-28 |
JP5230997B2 (ja) | 2013-07-10 |
KR101498736B1 (ko) | 2015-03-04 |
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