JP2008514018A5 - - Google Patents

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Publication number
JP2008514018A5
JP2008514018A5 JP2007532649A JP2007532649A JP2008514018A5 JP 2008514018 A5 JP2008514018 A5 JP 2008514018A5 JP 2007532649 A JP2007532649 A JP 2007532649A JP 2007532649 A JP2007532649 A JP 2007532649A JP 2008514018 A5 JP2008514018 A5 JP 2008514018A5
Authority
JP
Japan
Prior art keywords
metal silicide
refractory metal
forming
silicide layer
subcollector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007532649A
Other languages
English (en)
Japanese (ja)
Other versions
JP5090168B2 (ja
JP2008514018A (ja
Filing date
Publication date
Priority claimed from US10/711,479 external-priority patent/US7002190B1/en
Application filed filed Critical
Publication of JP2008514018A publication Critical patent/JP2008514018A/ja
Publication of JP2008514018A5 publication Critical patent/JP2008514018A5/ja
Application granted granted Critical
Publication of JP5090168B2 publication Critical patent/JP5090168B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007532649A 2004-09-21 2005-09-20 ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法） Expired - Fee Related JP5090168B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/711,479 2004-09-21
US10/711,479 US7002190B1 (en) 2004-09-21 2004-09-21 Method of collector formation in BiCMOS technology
PCT/US2005/033851 WO2006034355A2 (en) 2004-09-21 2005-09-20 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY

Publications (3)

Publication Number Publication Date
JP2008514018A JP2008514018A (ja) 2008-05-01
JP2008514018A5 true JP2008514018A5 (enExample) 2008-09-18
JP5090168B2 JP5090168B2 (ja) 2012-12-05

Family

ID=35810621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007532649A Expired - Fee Related JP5090168B2 (ja) 2004-09-21 2005-09-20 ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法）

Country Status (7)

Country Link
US (2) US7002190B1 (enExample)
EP (1) EP1794806B1 (enExample)
JP (1) JP5090168B2 (enExample)
KR (1) KR100961738B1 (enExample)
CN (1) CN101432892B (enExample)
TW (1) TWI364795B (enExample)
WO (1) WO2006034355A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200727367A (en) * 2005-04-22 2007-07-16 Icemos Technology Corp Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches
DE102005021932A1 (de) * 2005-05-12 2006-11-16 Atmel Germany Gmbh Verfahren zur Herstellung integrierter Schaltkreise
US8435873B2 (en) 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
JP5029607B2 (ja) 2006-07-28 2012-09-19 株式会社島津製作所 Ｘ線診断装置
US7709338B2 (en) * 2006-12-21 2010-05-04 International Business Machines Corporation BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices
US20090072355A1 (en) * 2007-09-17 2009-03-19 International Business Machines Corporation Dual shallow trench isolation structure
JP2009099815A (ja) * 2007-10-18 2009-05-07 Toshiba Corp 半導体装置の製造方法
US9059196B2 (en) 2013-11-04 2015-06-16 International Business Machines Corporation Bipolar junction transistors with self-aligned terminals
US9570564B2 (en) 2014-08-05 2017-02-14 Globalfoundries Inc. Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
CN108110051B (zh) * 2017-12-19 2019-11-12 上海华力微电子有限公司 一种带沟槽结构的双极型晶体管及其制作方法
US11640975B2 (en) 2021-06-17 2023-05-02 Nxp Usa, Inc. Silicided collector structure

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US4446476A (en) * 1981-06-30 1984-05-01 International Business Machines Corporation Integrated circuit having a sublayer electrical contact and fabrication thereof
JPS6021558A (ja) * 1983-07-15 1985-02-02 Mitsubishi Electric Corp バイポ−ラ型半導体集積回路装置
JPS60117664A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd バイポ−ラ半導体装置
US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US4949151A (en) 1986-09-24 1990-08-14 Hitachi, Ltd. Bipolar transistor having side wall base and collector contacts
JPS63278347A (ja) * 1987-05-11 1988-11-16 Toshiba Corp 半導体装置およびその製造方法
EP0306213A3 (en) * 1987-09-02 1990-05-30 AT&T Corp. Submicron bipolar transistor with edge contacts
JPH01146361A (ja) * 1987-12-02 1989-06-08 Fujitsu Ltd 半導体装置
US4987471A (en) * 1988-03-30 1991-01-22 At&T Bell Laboratories High-speed dielectrically isolated devices utilizing buried silicide regions
US4926233A (en) * 1988-06-29 1990-05-15 Texas Instruments Incorporated Merged trench bipolar-CMOS transistor fabrication process
JPH0389524A (ja) * 1989-08-31 1991-04-15 Fujitsu Ltd 半導体装置及びその製造方法
US5061646A (en) 1990-06-29 1991-10-29 Motorola, Inc. Method for forming a self-aligned bipolar transistor
JPH04106932A (ja) * 1990-08-27 1992-04-08 Fujitsu Ltd バイポーラトランジスタの製造方法
US5256896A (en) * 1991-08-30 1993-10-26 International Business Machines Corporation Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor
KR100257517B1 (ko) * 1997-07-01 2000-06-01 윤종용 고속 바이폴라 트랜지스터 및 그 제조방법
US6960818B1 (en) * 1997-12-30 2005-11-01 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
JPH11312687A (ja) * 1998-04-30 1999-11-09 Toshiba Corp 半導体装置およびその製造方法
DE19842106A1 (de) 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
US6251738B1 (en) * 2000-01-10 2001-06-26 International Business Machines Corporation Process for forming a silicon-germanium base of heterojunction bipolar transistor
US6333235B1 (en) 2000-04-12 2001-12-25 Industrial Technologyresearch Institute Method for forming SiGe bipolar transistor
US6271068B1 (en) 2001-01-08 2001-08-07 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits
US6686252B2 (en) * 2001-03-10 2004-02-03 International Business Machines Corporation Method and structure to reduce CMOS inter-well leakage
US20050250289A1 (en) * 2002-10-30 2005-11-10 Babcock Jeffrey A Control of dopant diffusion from buried layers in bipolar integrated circuits
US6878976B2 (en) * 2002-03-13 2005-04-12 International Business Machines Corporation Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications
JP2003303830A (ja) 2002-04-12 2003-10-24 Nec Electronics Corp 半導体装置及びその製造方法
US6630377B1 (en) 2002-09-18 2003-10-07 Chartered Semiconductor Manufacturing Ltd. Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
US7233498B2 (en) 2002-09-27 2007-06-19 Eastman Kodak Company Medium having data storage and communication capabilities and method for forming same
FR2845522A1 (fr) * 2002-10-03 2004-04-09 St Microelectronics Sa Circuit integre a couche enterree fortement conductrice
JP3643100B2 (ja) * 2002-10-04 2005-04-27 松下電器産業株式会社 半導体装置
JP3507830B1 (ja) * 2002-10-04 2004-03-15 松下電器産業株式会社 半導体装置
KR100486304B1 (ko) 2003-02-07 2005-04-29 삼성전자주식회사 자기정렬을 이용한 바이씨모스 제조방법

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