US20090230484A1 - Method of fabricating a semiconductor device - Google Patents

Method of fabricating a semiconductor device Download PDF

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US20090230484A1
US20090230484A1 US12/474,185 US47418509A US2009230484A1 US 20090230484 A1 US20090230484 A1 US 20090230484A1 US 47418509 A US47418509 A US 47418509A US 2009230484 A1 US2009230484 A1 US 2009230484A1
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gate electrode
oxide layer
layer
sidewalls
semiconductor substrate
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US12/474,185
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Jung-Hak Myung
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET

Definitions

  • Resistance of a gate electrode may be an important factor in determining an operational speed of a semiconductor device.
  • a silicide layer may be formed on the poly gate electrode.
  • FIGS. 1A to 1G are example sectional diagrams illustrating a method of fabricating a related art semiconductor device.
  • a gate electrode material such as polysilicon may be formed on silicon substrate 100 , and gate electrode material may be etched using a photoresist pattern as a mask. The photoresist pattern may be removed and a cleaning process may be performed thereon to form gate electrode 110 .
  • poly oxide layer 120 may be formed on a surface, for example the entire upper surface, of silicon substrate 100 including gate electrode 110 .
  • Poly oxide layer 120 may recover or correct damage caused by plasma generated during the etching process and may prevent damage that may be caused during an implant process that may be performed later.
  • Such an implant process may be an ion implant process to form an N lightly doped drain (LDD).
  • LDD lightly doped drain
  • cap oxide layer 130 may be formed on poly oxide layer 120 .
  • Cap oxide layer 130 may serve as an etch stop layer, and may prevent damage caused by an implant process to be performed after the ion implant process for forming an N LDD. Such an implant process may include an ion implant process for forming a P LDD.
  • Cap oxide layer 130 may also prevent damage caused during an etching process of a sidewall nitride.
  • Cap oxide layer 130 may be formed using a tetra ethyl ortho silicate (TEOS).
  • TEOS tetra ethyl ortho silicate
  • nitride layer 140 may be formed on a surface (for example, an entire upper surface) of cap oxide layer 130 .
  • Nitride layer 140 may be used to form sidewalls and may be formed using a deposition process.
  • nitride layer 140 may be etched to form sidewalls 141 and 142 at both sides of gate electrode 110 .
  • a source/drain implant process may then be performed.
  • poly oxide layer 120 and cap oxide layer 130 on silicon substrate 100 and gate electrode 110 may be removed, for example using dry and wet etching processes. This may be done before forming a silicide layer having lower specific resistance than specific resistance of a poly gate on a surface of silicon substrate 100 and a surface of gate electrode 110 in order to reduce resistance of a poly gate.
  • silicide layer 150 may be formed on an exposed surface of substrate 100 and an exposed surface of the gate electrode.
  • Silicide layer 150 may be formed by depositing a metal layer such as a Co layer, a Ti layer, and/or a Ni layer on a surface of the structure illustrated in FIG. 1F , for example using a sputtering process and then performing a patterning process, a stripping process, a heat treatment process, and the like.
  • a silicide layer having lower specific resistance than specific resistance of a poly gate may be formed on an exposed surface of a substrate and a gate, resistance of a poly gate may be reduced.
  • the silicide layer may be formed on only the upper surface of the gate, there may be a limitation in reducing resistance.
  • Embodiments relate to a method of fabricating a semiconductor device. Embodiments relate to a method of fabricating a gate of a semiconductor device.
  • Embodiments relate a method of fabricating a semiconductor device capable of reducing gate resistance by enlarging a silicide layer formed on a gate.
  • a method of fabricating a semiconductor device may include forming a gate electrode on a semiconductor substrate, forming an insulating layer on the semiconductor substrate including the gate electrode, forming height differences in both edge portions of the insulating layer, etching the insulating layer with the height differences to form sidewalls at both sides of the gate electrode, and forming a silicide layer on an exposed surface of the gate electrode and a portion of the semiconductor substrate at both sides of the side walls.
  • forming of the height differences may include forming a photoresist pattern on the insulating layer, etching the insulating layer using the photoresist pattern as a mask, and removing the photoresist pattern.
  • the photoresist pattern may expose only a portion of the insulating layer where the sidewalls may be formed.
  • the photoresist pattern may include a first pattern that may be formed to have a width corresponding to a width of the gate electrode on the gate electrode and second patterns that are spaced apart from both sides of the first pattern by a width of the sidewalls.
  • the insulating layer may be formed of a nitride.
  • a semiconductor device may include a semiconductor substrate, a gate electrode formed on the semiconductor substrate, an oxide layer formed to a lower height than a height of the gate electrode at a side of the gate electrode, a sidewall formed on the oxide layer, and a silicide layer covering the semiconductor substrate and an upper surface and a portion of a side surface of the gate electrode.
  • the oxide layer may include a poly oxide layer and a cap oxide layer.
  • FIGS. 1A to 1G are example sectional diagrams illustrating a related art method of fabricating a semiconductor device
  • FIGS. 2A to 2I are example sectional diagrams illustrating a method of fabricating a semiconductor device according to embodiments.
  • a gate electrode material such as polysilicon may be formed on silicon substrate 200 .
  • the gate electrode material may be etched using a photoresist pattern as a mask.
  • the photoresist pattern may be removed, and a cleaning process may be performed thereon to form gate electrode 210 .
  • poly oxide layer 220 may be formed on a surface (for example, the entire upper surface) of silicon substrate 200 , including gate electrode 210 .
  • Poly oxide layer 220 may correct or recover damage caused by plasma generated during the etching process.
  • Poly oxide layer 220 may also prevent damage that may be caused during an implant process to be performed later.
  • such an implant process may include an ion implant process for forming an N LDD.
  • cap oxide layer 230 may be formed on poly oxide layer 220 .
  • Cap oxide layer 230 may serve as an etch stop layer and may prevent damage caused by an implant process that may be performed after the ion implant process for forming an N LDD, for example, an ion implant process for forming a P LDD.
  • Cap oxide layer 230 may also prevent incidental damage caused during an etching process of a sidewall nitride.
  • Cap oxide layer 230 may be formed using a tetra ethyl ortho silicate (TEOS).
  • TEOS tetra ethyl ortho silicate
  • nitride layer 240 which may serve as an insulating layer, may be formed on a whole upper surface of cap oxide layer 230 .
  • Nitride layer 240 may be used to form sidewalls, and may be formed using a deposition process.
  • nitride layer 240 may be coated with a photoresist layer, and exposure and development processes may be performed thereon to form photoresist pattern 250 .
  • Photoresist pattern 250 may be formed to expose only portions of nitride layer 240 in which sidewalls may be formed.
  • photoresist pattern 250 may include first pattern 251 , which may be formed on gate electrode 210 to have a width corresponding to a width of gate electrode 210 , and second patterns 252 , which may be spaced apart from both sides of first pattern 251 by a width of the sidewalls.
  • the exposed portion of nitride layer 240 may be etched using photoresist pattern 250 as a mask to form height differences at edge portions of nitride layer 240 .
  • photoresist pattern 250 may be removed to expose nitride layer 241 with the height differences.
  • nitride layer 241 may be anisotropically etched to form sidewalls 242 and 243 at both sides of gate electrode 210 .
  • a height of sidewalls 242 and 243 may be lower than a height of related art sidewalls and may have a same width as a width of related art sidewalls. Consequently, sidewalls 242 and 243 may be formed to a height lower than a height of gate electrode 210 .
  • an exposed portion of poly oxide layer 220 and cap oxide layer 230 may be removed using an etching process.
  • a portion where a silicide layer may be formed may be pre-cleaned using HF.
  • silicide layer 260 may be formed on an exposed portion of gate electrode 210 , that is, an upper surface and an upper portion of side surfaces of gate electrode 210 .
  • a silicide layer formed on a gate may be enlarged in both lateral directions, which may reduce gate resistance. This may improve an operational speed of the semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance.

Description

  • The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0133888 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety.
    • BACKGROUND
  • Resistance of a gate electrode may be an important factor in determining an operational speed of a semiconductor device. To reduce resistance of a poly gate electrode, for example, a silicide layer may be formed on the poly gate electrode.
  • FIGS. 1A to 1G are example sectional diagrams illustrating a method of fabricating a related art semiconductor device.
  • Referring to FIG. 1A, a gate electrode material such as polysilicon may be formed on silicon substrate 100, and gate electrode material may be etched using a photoresist pattern as a mask. The photoresist pattern may be removed and a cleaning process may be performed thereon to form gate electrode 110.
  • Referring to FIG. 1B, poly oxide layer 120 may be formed on a surface, for example the entire upper surface, of silicon substrate 100 including gate electrode 110. Poly oxide layer 120 may recover or correct damage caused by plasma generated during the etching process and may prevent damage that may be caused during an implant process that may be performed later. Such an implant process may be an ion implant process to form an N lightly doped drain (LDD).
  • Referring to FIG. 1C, cap oxide layer 130 may be formed on poly oxide layer 120. Cap oxide layer 130 may serve as an etch stop layer, and may prevent damage caused by an implant process to be performed after the ion implant process for forming an N LDD. Such an implant process may include an ion implant process for forming a P LDD. Cap oxide layer 130 may also prevent damage caused during an etching process of a sidewall nitride. Cap oxide layer 130 may be formed using a tetra ethyl ortho silicate (TEOS).
  • Referring to FIG. 1D, nitride layer 140 may be formed on a surface (for example, an entire upper surface) of cap oxide layer 130. Nitride layer 140 may be used to form sidewalls and may be formed using a deposition process.
  • Referring to FIG. 1E, nitride layer 140 may be etched to form sidewalls 141 and 142 at both sides of gate electrode 110. A source/drain implant process may then be performed.
  • Referring to FIG. 1F, poly oxide layer 120 and cap oxide layer 130 on silicon substrate 100 and gate electrode 110 may be removed, for example using dry and wet etching processes. This may be done before forming a silicide layer having lower specific resistance than specific resistance of a poly gate on a surface of silicon substrate 100 and a surface of gate electrode 110 in order to reduce resistance of a poly gate.
  • Referring to FIG. 1G, silicide layer 150 may be formed on an exposed surface of substrate 100 and an exposed surface of the gate electrode. Silicide layer 150 may be formed by depositing a metal layer such as a Co layer, a Ti layer, and/or a Ni layer on a surface of the structure illustrated in FIG. 1F, for example using a sputtering process and then performing a patterning process, a stripping process, a heat treatment process, and the like.
  • According to the above-mentioned method of related art, as a silicide layer having lower specific resistance than specific resistance of a poly gate may be formed on an exposed surface of a substrate and a gate, resistance of a poly gate may be reduced. However, since the silicide layer may be formed on only the upper surface of the gate, there may be a limitation in reducing resistance.
    • SUMMARY
  • Embodiments relate to a method of fabricating a semiconductor device. Embodiments relate to a method of fabricating a gate of a semiconductor device.
  • Embodiments relate a method of fabricating a semiconductor device capable of reducing gate resistance by enlarging a silicide layer formed on a gate.
  • According to embodiments, a method of fabricating a semiconductor device may include forming a gate electrode on a semiconductor substrate, forming an insulating layer on the semiconductor substrate including the gate electrode, forming height differences in both edge portions of the insulating layer, etching the insulating layer with the height differences to form sidewalls at both sides of the gate electrode, and forming a silicide layer on an exposed surface of the gate electrode and a portion of the semiconductor substrate at both sides of the side walls.
  • According to embodiments, forming of the height differences may include forming a photoresist pattern on the insulating layer, etching the insulating layer using the photoresist pattern as a mask, and removing the photoresist pattern.
  • According to embodiments, the photoresist pattern may expose only a portion of the insulating layer where the sidewalls may be formed.
  • According to embodiments, the photoresist pattern may include a first pattern that may be formed to have a width corresponding to a width of the gate electrode on the gate electrode and second patterns that are spaced apart from both sides of the first pattern by a width of the sidewalls.
  • According to embodiments, the insulating layer may be formed of a nitride.
  • According to embodiments, a semiconductor device may include a semiconductor substrate, a gate electrode formed on the semiconductor substrate, an oxide layer formed to a lower height than a height of the gate electrode at a side of the gate electrode, a sidewall formed on the oxide layer, and a silicide layer covering the semiconductor substrate and an upper surface and a portion of a side surface of the gate electrode.
  • According to embodiments, the oxide layer may include a poly oxide layer and a cap oxide layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1G are example sectional diagrams illustrating a related art method of fabricating a semiconductor device;
  • FIGS. 2A to 2I are example sectional diagrams illustrating a method of fabricating a semiconductor device according to embodiments.
    •  DETAILED DESCRIPTION
  • Referring to FIG. 2A, a gate electrode material such as polysilicon may be formed on silicon substrate 200. The gate electrode material may be etched using a photoresist pattern as a mask. The photoresist pattern may be removed, and a cleaning process may be performed thereon to form gate electrode 210.
  • Referring to FIG. 2B, poly oxide layer 220 may be formed on a surface (for example, the entire upper surface) of silicon substrate 200, including gate electrode 210. Poly oxide layer 220 may correct or recover damage caused by plasma generated during the etching process. Poly oxide layer 220 may also prevent damage that may be caused during an implant process to be performed later. In embodiments, such an implant process may include an ion implant process for forming an N LDD.
  • Referring to FIG. 2C, cap oxide layer 230 may be formed on poly oxide layer 220. Cap oxide layer 230 may serve as an etch stop layer and may prevent damage caused by an implant process that may be performed after the ion implant process for forming an N LDD, for example, an ion implant process for forming a P LDD. Cap oxide layer 230 may also prevent incidental damage caused during an etching process of a sidewall nitride. Cap oxide layer 230 may be formed using a tetra ethyl ortho silicate (TEOS).
  • Referring to FIG. 2D, nitride layer 240, which may serve as an insulating layer, may be formed on a whole upper surface of cap oxide layer 230. Nitride layer 240 may be used to form sidewalls, and may be formed using a deposition process.
  • Referring to FIG. 2E, nitride layer 240 may be coated with a photoresist layer, and exposure and development processes may be performed thereon to form photoresist pattern 250. Photoresist pattern 250 may be formed to expose only portions of nitride layer 240 in which sidewalls may be formed. In embodiments, photoresist pattern 250 may include first pattern 251, which may be formed on gate electrode 210 to have a width corresponding to a width of gate electrode 210, and second patterns 252, which may be spaced apart from both sides of first pattern 251 by a width of the sidewalls. Next, the exposed portion of nitride layer 240 may be etched using photoresist pattern 250 as a mask to form height differences at edge portions of nitride layer 240.
  • Referring to FIG. 2F, photoresist pattern 250 may be removed to expose nitride layer 241 with the height differences.
  • Referring to FIG. 2G, nitride layer 241 may be anisotropically etched to form sidewalls 242 and 243 at both sides of gate electrode 210. As nitride layer 241 is anisotropically etched, due to the height difference formed at both edge portions of nitride layer 241, a height of sidewalls 242 and 243 may be lower than a height of related art sidewalls and may have a same width as a width of related art sidewalls. Consequently, sidewalls 242 and 243 may be formed to a height lower than a height of gate electrode 210.
  • Referring to FIG. 2H, an exposed portion of poly oxide layer 220 and cap oxide layer 230, for example, poly oxide layer 220 and cap oxide layer 230 formed on an upper surface and an upper portion of side surfaces of gate electrode 210 and silicon substrate 200, may be removed using an etching process. Next, a portion where a silicide layer may be formed may be pre-cleaned using HF.
  • Referring to FIG. 2I, silicide layer 260 may be formed on an exposed portion of gate electrode 210, that is, an upper surface and an upper portion of side surfaces of gate electrode 210.
  • According to a method of fabricating a semiconductor device in embodiments, a silicide layer formed on a gate may be enlarged in both lateral directions, which may reduce gate resistance. This may improve an operational speed of the semiconductor device.
  • It will be apparent to those skilled in the art that various modifications and variations may be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims. It also understood that when a layer is referred to as being “on” or “over” another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present.

Claims (7)

1-20. (canceled)
21. A device, comprising:
a semiconductor substrate;
a gate electrode formed over the semiconductor substrate;
an oxide layer having a height lower than a height of the gate electrode at sides of the gate electrode;
a sidewall formed over the oxide layer; and
a silicide layer covering a top surface of the gate electrode and a portion of a side surface of the gate electrode,
wherein a width of the combined silicide layer is greater than a width of the gate electrode.
22. The device of claim 21, wherein the silicide layer further covers the semiconductor substrate.
23. The device of claim 21, wherein the silicide layer covers the top surface of the gate electrode and a top surface of the oxide layer to form a combined silicide layer.
24. The device of claim 21, wherein the oxide layer comprises a poly oxide layer and a cap oxide layer.
25. A device comprising:
a gate electrode having first height formed on a semiconductor substrate;
sidewalls having a second height formed on the semiconductor substrate adjacent to the gate;
a silicide layer formed on a top surface of the gate electrode and at least a portion of a top surface of the sidewalls,
wherein the silicide layer is formed on the oxide layer adjacent to the sidewalls and on a side portion of the gate electrode,
wherein the silicide layer over the gate electrode and over the oxide layer forms a single surface having a width greater than a width of the gate electrode.
26. The device of claim 25, wherein the sidewalls comprise an oxide layer formed directly adjacent to the sidewalls and over a portion of the semiconductor substrate, and a nitride layer formed over the oxide layer.
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US6169017B1 (en) * 1999-11-23 2001-01-02 United Silicon Incorporated Method to increase contact area
US20040132274A1 (en) * 2003-01-08 2004-07-08 Samsung Electronics Co., Ltd. Method of forming thick metal silicide layer on gate electrode

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