JP2008514018A - ヘテロバイポーラ・トランジスタ(HBT)およびその製作方法(BiCMOS技術におけるコレクタ形成方法) - Google Patents
ヘテロバイポーラ・トランジスタ(HBT)およびその製作方法(BiCMOS技術におけるコレクタ形成方法) Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 125000005842 heteroatom Chemical group 0.000 title abstract 2
- 238000005516 engineering process Methods 0.000 title description 3
- 239000003870 refractory metal Substances 0.000 claims abstract description 69
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 60
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000137 annealing Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 238000005137 deposition process Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910003811 SiGeC Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 229910003465 moissanite Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
- 238000000280 densification Methods 0.000 claims description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 36
- 150000004767 nitrides Chemical class 0.000 description 15
- 238000012545 processing Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000007654 immersion Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- -1 SOI Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
【解決手段】本発明のHBTは、少なくともサブコレクタ(13)を含む基板(12)と、サブコレクタ上に位置する埋め込み高融点金属シリサイド層(28)と、埋め込み高融点金属シリサイド層の表面上に位置するシャロー・トレンチ分離領域(30)とを含む。また、本発明の方法は、デバイスのサブコレクタ上のシャロー・トレンチ分離領域の下部に埋め込み高融点金属シリサイド層を形成するステップを含む。
【選択図】図6
Description
Claims (30)
- 少なくともサブコレクタを含む基板と、
前記サブコレクタ上に位置する埋め込み高融点金属シリサイド層と、
前記埋め込み高融点金属シリサイド層の表面上に位置するシャロー・トレンチ分離領域とを有する、ヘテロバイポーラ・トランジスタ(HBT)。 - 前記基板が、Si、SiGe、SiC、SiGeC、GaAs、InAs、InP、シリコン・オン・インシュレータ、シリコン・ゲルマニウム・オン・インシュレータ、および他のIII−V族、またはII−VI族化合物半導体からなる群から選択された半導体基板を有する、請求項1に記載のHBT。
- 前記半導体基板がSiを含有する、請求項2に記載のHBT。
- 前記サブコレクタがCでドープされている、請求項1に記載のHBT。
- 前記シャロー・トレンチ分離領域、および前記埋め込み高融点金属シリサイド層が、窒化物スペーサまたは酸窒化物スペーサを有する開口部内に位置する、請求項1に記載のHBT。
- 前記高融点金属シリサイド層が、Ti、Co、W、Ta、Ni、またはそれらの合金のシリサイドを含む、請求項1に記載のHBT。
- 前記高融点金属シリサイド層が、Co、Ta、またはWのシリサイドを含む、請求項6に記載のHBT。
- 前記高融点金属シリサイド層が、Wのシリサイドを含む、請求項7に記載のHBT。
- 前記シャロー・トレンチ分離領域がトレンチ誘電体を含む、請求項1に記載のHBT。
- 前記高融点金属シリサイド層が前記シャロー・トレンチ分離領域の縁端部から突出して、前記高融点金属シリサイド層の一部がアンダーカット領域内に存在するようになされている、請求項1に記載のHBT。
- 前記高融点金属シリサイド層が、Ti、Co、W、Ta、Ni、またはそれらの合金のシリサイドを含む、請求項10に記載のHBT。
- 前記高融点金属シリサイド層が、Co、Ta、またはWのシリサイドを含む、請求項11に記載のHBT。
- 前記高融点金属シリサイド層が、Wのシリサイドを含む、請求項12に記載のHBT。
- 前記サブコレクタを含む前記基板上に位置するSiGeベースおよびポリSiエミッタをさらに有する、請求項1に記載のHBT。
- サブコレクタを含む基板内に、第1のトレンチ誘電体を含む少なくとも1つのシャロー・トレンチ分離領域を形成するステップと、
前記少なくとも1つのシャロー・トレンチ分離領域から前記第1のトレンチ誘電体を除去して、前記サブコレクタを含む前記基板の一部を露出する開口部を形成するステップと、
前記基板の前記露出部上の前記開口部の一部内に、前記開口部の上方に突出しない高融点金属シリサイド層を形成するステップと、
前記開口部内の前記高融点金属シリサイド層上に、前記開口部の上方に突出しない第2のトレンチ誘電体を形成するステップとを有する、
ヘテロバイポーラ・トランジスタ(HBT)を製作する方法。 - 前記少なくとも1つのシャロー・トレンチ分離領域が、リソグラフィ、エッチング、およびトレンチ充填により形成される、請求項15に記載の方法。
- 高密度化プロセスまたは平坦化プロセスのうちの少なくとも1つをさらに有する、請求項16に記載の方法。
- トレンチ充填の前に前記サブコレクタにCを注入するステップをさらに有する、請求項16に記載の方法。
- 前記第1のトレンチ誘電体の前記除去ステップが、選択的エッチング・プロセスを含む、請求項15に記載の方法。
- 前記第1のトレンチ誘電体を除去するステップと前記高融点金属シリサイドを形成するステップとの間に、窒化物スペーサまたは酸窒化物スペーサを形成するステップをさらに有する、請求項15に記載の方法。
- 前記高融点金属シリサイド層を前記形成するステップが、高融点金属層を堆積させるステップと、アニーリングするステップとを含む、請求項15に記載の方法。
- 堆積ステップの前にシリコン層を形成するステップをさらに含む、請求項21に記載の方法。
- 前記堆積ステップが選択的堆積プロセスを含む、請求項21に記載の方法。
- 前記堆積ステップが非選択的堆積プロセスを含む、請求項21に記載の方法。
- 前記アニーリング・ステップが、第1のアニーリング・ステップと、未反応の高融点金属を除去するステップとを含む、請求項21に記載の方法。
- 前記第1のアニーリング・ステップが、約400℃から約700℃までの温度で実行される、請求項25に記載の方法。
- 未反応の高融点金属の前記除去ステップ後に実行される第2のアニーリング・ステップをさらに有する、請求項21に記載の方法。
- 前記第2のアニーリング・ステップが、約700℃から約1100℃までの温度で実行される、請求項27に記載の方法。
- 前記第1のトレンチ誘電体を前記除去するステップが、前記少なくとも1つのシャロー・トレンチ分離領域の一部を保護するパターン化したフォトレジストを形成するステップを含む、請求項15に記載の方法。
- 横方向エッチング・プロセスを用いて、アンダーカット領域を形成するステップをさらに有する、請求項29に記載の方法。
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US10/711,479 | 2004-09-21 | ||
US10/711,479 US7002190B1 (en) | 2004-09-21 | 2004-09-21 | Method of collector formation in BiCMOS technology |
PCT/US2005/033851 WO2006034355A2 (en) | 2004-09-21 | 2005-09-20 | METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY |
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CN (1) | CN101432892B (ja) |
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JP2009099815A (ja) * | 2007-10-18 | 2009-05-07 | Toshiba Corp | 半導体装置の製造方法 |
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KR20080028858A (ko) * | 2005-04-22 | 2008-04-02 | 아이스모스 테크날러지 코포레이션 | 산화물 라인드 트렌치를 갖는 슈퍼 접합 장치 및 그 제조방법 |
DE102005021932A1 (de) * | 2005-05-12 | 2006-11-16 | Atmel Germany Gmbh | Verfahren zur Herstellung integrierter Schaltkreise |
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WO2008013255A1 (fr) | 2006-07-28 | 2008-01-31 | Shimadzu Corporation | APPAREIL radiographique |
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WO2006034355A2 (en) | 2006-03-30 |
KR20070053280A (ko) | 2007-05-23 |
US7491985B2 (en) | 2009-02-17 |
US20060124964A1 (en) | 2006-06-15 |
CN101432892B (zh) | 2010-08-25 |
CN101432892A (zh) | 2009-05-13 |
TW200614383A (en) | 2006-05-01 |
US7002190B1 (en) | 2006-02-21 |
KR100961738B1 (ko) | 2010-06-10 |
WO2006034355A3 (en) | 2009-04-16 |
EP1794806A4 (en) | 2011-06-29 |
JP5090168B2 (ja) | 2012-12-05 |
EP1794806A2 (en) | 2007-06-13 |
EP1794806B1 (en) | 2014-07-02 |
TWI364795B (en) | 2012-05-21 |
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