JP5090168B2 - ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法） - Google Patents

ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法） Download PDF

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JP5090168B2
JP5090168B2 JP2007532649A JP2007532649A JP5090168B2 JP 5090168 B2 JP5090168 B2 JP 5090168B2 JP 2007532649 A JP2007532649 A JP 2007532649A JP 2007532649 A JP2007532649 A JP 2007532649A JP 5090168 B2 JP5090168 B2 JP 5090168B2
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opening
refractory metal
hbt
subcollector
metal silicide
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Expired - Fee Related
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JP2007532649A
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Japanese (ja)
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JP2008514018A5 (enExample
JP2008514018A (ja
Inventor
ガイス、ピーター、ジェイ
グレイ、ピーター、ビー
ジョセフ、アルヴィン、ジェイ
リウ、チージー
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
JP2007532649A 2004-09-21 2005-09-20 ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法） Expired - Fee Related JP5090168B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/711,479 2004-09-21
US10/711,479 US7002190B1 (en) 2004-09-21 2004-09-21 Method of collector formation in BiCMOS technology
PCT/US2005/033851 WO2006034355A2 (en) 2004-09-21 2005-09-20 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY

Publications (3)

Publication Number Publication Date
JP2008514018A JP2008514018A (ja) 2008-05-01
JP2008514018A5 JP2008514018A5 (enExample) 2008-09-18
JP5090168B2 true JP5090168B2 (ja) 2012-12-05

Family

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Family Applications (1)

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JP2007532649A Expired - Fee Related JP5090168B2 (ja) 2004-09-21 2005-09-20 ヘテロバイポーラ・トランジスタ（ＨＢＴ）およびその製作方法（ＢｉＣＭＯＳ技術におけるコレクタ形成方法）

Country Status (7)

Country Link
US (2) US7002190B1 (enExample)
EP (1) EP1794806B1 (enExample)
JP (1) JP5090168B2 (enExample)
KR (1) KR100961738B1 (enExample)
CN (1) CN101432892B (enExample)
TW (1) TWI364795B (enExample)
WO (1) WO2006034355A2 (enExample)

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TW200727367A (en) * 2005-04-22 2007-07-16 Icemos Technology Corp Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches
DE102005021932A1 (de) * 2005-05-12 2006-11-16 Atmel Germany Gmbh Verfahren zur Herstellung integrierter Schaltkreise
US8435873B2 (en) 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
JP5029607B2 (ja) 2006-07-28 2012-09-19 株式会社島津製作所 Ｘ線診断装置
US7709338B2 (en) * 2006-12-21 2010-05-04 International Business Machines Corporation BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices
US20090072355A1 (en) * 2007-09-17 2009-03-19 International Business Machines Corporation Dual shallow trench isolation structure
JP2009099815A (ja) * 2007-10-18 2009-05-07 Toshiba Corp 半導体装置の製造方法
US9059196B2 (en) 2013-11-04 2015-06-16 International Business Machines Corporation Bipolar junction transistors with self-aligned terminals
US9570564B2 (en) 2014-08-05 2017-02-14 Globalfoundries Inc. Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
CN108110051B (zh) * 2017-12-19 2019-11-12 上海华力微电子有限公司 一种带沟槽结构的双极型晶体管及其制作方法
US11640975B2 (en) 2021-06-17 2023-05-02 Nxp Usa, Inc. Silicided collector structure

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JPS60117664A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd バイポ−ラ半導体装置
US4589193A (en) * 1984-06-29 1986-05-20 International Business Machines Corporation Metal silicide channel stoppers for integrated circuits and method for making the same
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US4949151A (en) 1986-09-24 1990-08-14 Hitachi, Ltd. Bipolar transistor having side wall base and collector contacts
JPS63278347A (ja) * 1987-05-11 1988-11-16 Toshiba Corp 半導体装置およびその製造方法
EP0306213A3 (en) * 1987-09-02 1990-05-30 AT&T Corp. Submicron bipolar transistor with edge contacts
JPH01146361A (ja) * 1987-12-02 1989-06-08 Fujitsu Ltd 半導体装置
US4987471A (en) * 1988-03-30 1991-01-22 At&T Bell Laboratories High-speed dielectrically isolated devices utilizing buried silicide regions
US4926233A (en) * 1988-06-29 1990-05-15 Texas Instruments Incorporated Merged trench bipolar-CMOS transistor fabrication process
JPH0389524A (ja) * 1989-08-31 1991-04-15 Fujitsu Ltd 半導体装置及びその製造方法
US5061646A (en) 1990-06-29 1991-10-29 Motorola, Inc. Method for forming a self-aligned bipolar transistor
JPH04106932A (ja) * 1990-08-27 1992-04-08 Fujitsu Ltd バイポーラトランジスタの製造方法
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US6960818B1 (en) * 1997-12-30 2005-11-01 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
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Also Published As

Publication number Publication date
TW200614383A (en) 2006-05-01
CN101432892A (zh) 2009-05-13
WO2006034355A2 (en) 2006-03-30
WO2006034355A3 (en) 2009-04-16
EP1794806B1 (en) 2014-07-02
CN101432892B (zh) 2010-08-25
US20060124964A1 (en) 2006-06-15
EP1794806A4 (en) 2011-06-29
TWI364795B (en) 2012-05-21
EP1794806A2 (en) 2007-06-13
JP2008514018A (ja) 2008-05-01
US7491985B2 (en) 2009-02-17
KR100961738B1 (ko) 2010-06-10
KR20070053280A (ko) 2007-05-23
US7002190B1 (en) 2006-02-21

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