JP2007525850A5 - - Google Patents

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Publication number
JP2007525850A5
JP2007525850A5 JP2007501778A JP2007501778A JP2007525850A5 JP 2007525850 A5 JP2007525850 A5 JP 2007525850A5 JP 2007501778 A JP2007501778 A JP 2007501778A JP 2007501778 A JP2007501778 A JP 2007501778A JP 2007525850 A5 JP2007525850 A5 JP 2007525850A5
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JP
Japan
Prior art keywords
gate
sidewall spacer
forming
channel transistor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007501778A
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English (en)
Japanese (ja)
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JP2007525850A (ja
JP4777335B2 (ja
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Publication date
Priority claimed from US10/790,420 external-priority patent/US7064396B2/en
Application filed filed Critical
Publication of JP2007525850A publication Critical patent/JP2007525850A/ja
Publication of JP2007525850A5 publication Critical patent/JP2007525850A5/ja
Application granted granted Critical
Publication of JP4777335B2 publication Critical patent/JP4777335B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007501778A 2004-03-01 2005-01-21 複合スペーサ絶縁領域幅を備えた集積回路の製造方法 Expired - Fee Related JP4777335B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/790,420 US7064396B2 (en) 2004-03-01 2004-03-01 Integrated circuit with multiple spacer insulating region widths
US10/790,420 2004-03-01
PCT/US2005/001916 WO2005091758A2 (en) 2004-03-01 2005-01-21 Integrated circuit with multiple spacer insulating region widths

Publications (3)

Publication Number Publication Date
JP2007525850A JP2007525850A (ja) 2007-09-06
JP2007525850A5 true JP2007525850A5 (enExample) 2008-03-06
JP4777335B2 JP4777335B2 (ja) 2011-09-21

Family

ID=34887473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007501778A Expired - Fee Related JP4777335B2 (ja) 2004-03-01 2005-01-21 複合スペーサ絶縁領域幅を備えた集積回路の製造方法

Country Status (7)

Country Link
US (2) US7064396B2 (enExample)
EP (1) EP1776719A4 (enExample)
JP (1) JP4777335B2 (enExample)
KR (1) KR101129070B1 (enExample)
CN (1) CN1926693B (enExample)
TW (1) TWI367520B (enExample)
WO (1) WO2005091758A2 (enExample)

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JP5435720B2 (ja) * 2009-12-21 2014-03-05 パナソニック株式会社 半導体装置
US8405160B2 (en) 2010-05-26 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-strained source/drain structures
US8552503B2 (en) 2010-11-30 2013-10-08 United Microelectronics Corp. Strained silicon structure
CN102543990B (zh) * 2010-12-15 2015-09-09 联华电子股份有限公司 应变硅半导体结构
US8440530B2 (en) * 2011-10-18 2013-05-14 Globalfoundries Inc. Methods of forming highly scaled semiconductor devices using a disposable spacer technique
CN103811420B (zh) * 2012-11-08 2016-12-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制备方法
US9196712B1 (en) 2014-09-12 2015-11-24 Globalfoundries Inc. FinFET extension regions
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WO2019221706A1 (en) 2018-05-15 2019-11-21 Hewlett-Packard Development Company, L.P. Fluidic die with monitoring circuit fault protection structure

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