CN1926693B - 具有多种隔离体绝缘区宽度的集成电路 - Google Patents
具有多种隔离体绝缘区宽度的集成电路 Download PDFInfo
- Publication number
- CN1926693B CN1926693B CN2005800068126A CN200580006812A CN1926693B CN 1926693 B CN1926693 B CN 1926693B CN 2005800068126 A CN2005800068126 A CN 2005800068126A CN 200580006812 A CN200580006812 A CN 200580006812A CN 1926693 B CN1926693 B CN 1926693B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0184—Manufacturing their gate sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/790,420 US7064396B2 (en) | 2004-03-01 | 2004-03-01 | Integrated circuit with multiple spacer insulating region widths |
| US10/790,420 | 2004-03-01 | ||
| PCT/US2005/001916 WO2005091758A2 (en) | 2004-03-01 | 2005-01-21 | Integrated circuit with multiple spacer insulating region widths |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1926693A CN1926693A (zh) | 2007-03-07 |
| CN1926693B true CN1926693B (zh) | 2010-10-20 |
Family
ID=34887473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005800068126A Expired - Fee Related CN1926693B (zh) | 2004-03-01 | 2005-01-21 | 具有多种隔离体绝缘区宽度的集成电路 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7064396B2 (enExample) |
| EP (1) | EP1776719A4 (enExample) |
| JP (1) | JP4777335B2 (enExample) |
| KR (1) | KR101129070B1 (enExample) |
| CN (1) | CN1926693B (enExample) |
| TW (1) | TWI367520B (enExample) |
| WO (1) | WO2005091758A2 (enExample) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050275034A1 (en) * | 2004-04-08 | 2005-12-15 | International Business Machines Corporation | A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance |
| US8669145B2 (en) * | 2004-06-30 | 2014-03-11 | International Business Machines Corporation | Method and structure for strained FinFET devices |
| US7217647B2 (en) * | 2004-11-04 | 2007-05-15 | International Business Machines Corporation | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern |
| JP4746332B2 (ja) * | 2005-03-10 | 2011-08-10 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
| JP4515305B2 (ja) * | 2005-03-29 | 2010-07-28 | 富士通セミコンダクター株式会社 | pチャネルMOSトランジスタおよびその製造方法、半導体集積回路装置の製造方法 |
| DE102005030583B4 (de) * | 2005-06-30 | 2010-09-30 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement |
| US20070095739A1 (en) * | 2005-10-24 | 2007-05-03 | Nikon Corporation | Utility transfer apparatus, stage apparatus, exposure apparatus, and device manufacturing method |
| US20070281405A1 (en) * | 2006-06-02 | 2007-12-06 | International Business Machines Corporation | Methods of stressing transistor channel with replaced gate and related structures |
| US20070278541A1 (en) * | 2006-06-05 | 2007-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer engineering on CMOS devices |
| US20080142879A1 (en) * | 2006-12-14 | 2008-06-19 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system employing differential spacers |
| US7510923B2 (en) | 2006-12-19 | 2009-03-31 | Texas Instruments Incorporated | Slim spacer implementation to improve drive current |
| DE102007009916B4 (de) * | 2007-02-28 | 2012-02-23 | Advanced Micro Devices, Inc. | Verfahren zum Entfernen unterschiedlicher Abstandshalter durch einen nasschemischen Ätzprozess |
| JP2009026955A (ja) * | 2007-07-19 | 2009-02-05 | Panasonic Corp | 半導体装置及びその製造方法 |
| DE102007052220B4 (de) * | 2007-10-31 | 2015-04-09 | Globalfoundries Inc. | Verfahren zur Dotierstoffprofileinstellung für MOS-Bauelemente durch Anpassen einer Abstandshalterbreite vor der Implantation |
| JP5064289B2 (ja) * | 2008-04-17 | 2012-10-31 | パナソニック株式会社 | 半導体装置およびその製造方法 |
| JP2011029610A (ja) * | 2009-06-26 | 2011-02-10 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
| JP5268859B2 (ja) * | 2009-10-23 | 2013-08-21 | パナソニック株式会社 | 半導体装置 |
| JP5435720B2 (ja) * | 2009-12-21 | 2014-03-05 | パナソニック株式会社 | 半導体装置 |
| US8405160B2 (en) | 2010-05-26 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-strained source/drain structures |
| US8552503B2 (en) | 2010-11-30 | 2013-10-08 | United Microelectronics Corp. | Strained silicon structure |
| CN102543990B (zh) * | 2010-12-15 | 2015-09-09 | 联华电子股份有限公司 | 应变硅半导体结构 |
| US8440530B2 (en) * | 2011-10-18 | 2013-05-14 | Globalfoundries Inc. | Methods of forming highly scaled semiconductor devices using a disposable spacer technique |
| CN103811420B (zh) * | 2012-11-08 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制备方法 |
| US9196712B1 (en) | 2014-09-12 | 2015-11-24 | Globalfoundries Inc. | FinFET extension regions |
| KR102301249B1 (ko) * | 2015-11-16 | 2021-09-10 | 삼성전자주식회사 | 반도체 장치 |
| WO2019221706A1 (en) | 2018-05-15 | 2019-11-21 | Hewlett-Packard Development Company, L.P. | Fluidic die with monitoring circuit fault protection structure |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316302B1 (en) * | 1998-06-26 | 2001-11-13 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
| US20020164847A1 (en) * | 2001-05-04 | 2002-11-07 | Samsung Electronics Co., Ltd. | Method of forming a CMOS type semiconductor device |
| US6506642B1 (en) * | 2001-12-19 | 2003-01-14 | Advanced Micro Devices, Inc. | Removable spacer technique |
| US6512273B1 (en) * | 2000-01-28 | 2003-01-28 | Advanced Micro Devices, Inc. | Method and structure for improving hot carrier immunity for devices with very shallow junctions |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| US20030124864A1 (en) * | 2001-12-28 | 2003-07-03 | Hirofumi Komori | Semiconductor device and its manufacturing method |
| US20030181028A1 (en) * | 2002-03-19 | 2003-09-25 | Yeap Geoffrey C-F | Integrated circuit device and method therefor |
| CN1449585A (zh) * | 2000-11-22 | 2003-10-15 | 株式会社日立制作所 | 半导体器件及其制造方法 |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0218408A3 (en) * | 1985-09-25 | 1988-05-25 | Hewlett-Packard Company | Process for forming lightly-doped-grain (ldd) structure in integrated circuits |
| US5021354A (en) * | 1989-12-04 | 1991-06-04 | Motorola, Inc. | Process for manufacturing a semiconductor device |
| JPH05326552A (ja) * | 1992-03-19 | 1993-12-10 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
| US5461243A (en) | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
| JPH07201777A (ja) * | 1994-01-11 | 1995-08-04 | Toshiba Corp | 半導体装置の製造方法 |
| US5580804A (en) * | 1994-12-15 | 1996-12-03 | Advanced Micro Devices, Inc. | Method for fabricating true LDD devices in a MOS technology |
| US5869866A (en) * | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions |
| US5943565A (en) | 1997-09-05 | 1999-08-24 | Advanced Micro Devices, Inc. | CMOS processing employing separate spacers for independently optimized transistor performance |
| US5846857A (en) | 1997-09-05 | 1998-12-08 | Advanced Micro Devices, Inc. | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance |
| JP3884203B2 (ja) | 1998-12-24 | 2007-02-21 | 株式会社東芝 | 半導体装置の製造方法 |
| US6369438B1 (en) | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6348382B1 (en) * | 1999-09-09 | 2002-02-19 | Taiwan Semiconductor Manufacturing Company | Integration process to increase high voltage breakdown performance |
| US6316304B1 (en) * | 2000-07-12 | 2001-11-13 | Chartered Semiconductor Manufacturing Ltd. | Method of forming spacers of multiple widths |
| US6524935B1 (en) | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
| US6890835B1 (en) | 2000-10-19 | 2005-05-10 | International Business Machines Corporation | Layer transfer of low defect SiGe using an etch-back process |
| US20020100942A1 (en) | 2000-12-04 | 2002-08-01 | Fitzgerald Eugene A. | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
| JP2003031495A (ja) | 2001-07-12 | 2003-01-31 | Hitachi Ltd | 半導体装置用基板の製造方法および半導体装置の製造方法 |
| US6475870B1 (en) | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
| JP2003151991A (ja) * | 2001-08-23 | 2003-05-23 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US6794303B2 (en) * | 2002-07-18 | 2004-09-21 | Mosel Vitelic, Inc. | Two stage etching of silicon nitride to form a nitride spacer |
| US6806584B2 (en) * | 2002-10-21 | 2004-10-19 | International Business Machines Corporation | Semiconductor device structure including multiple fets having different spacer widths |
| JP4406200B2 (ja) * | 2002-12-06 | 2010-01-27 | 株式会社東芝 | 半導体装置 |
| US20040188765A1 (en) * | 2003-03-28 | 2004-09-30 | International Business Machines Corporation | Cmos device integration for low external resistance |
| US6902971B2 (en) * | 2003-07-21 | 2005-06-07 | Freescale Semiconductor, Inc. | Transistor sidewall spacer stress modulation |
| US7176137B2 (en) * | 2003-05-09 | 2007-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for multiple spacer width control |
| US7279746B2 (en) * | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
| US6890808B2 (en) * | 2003-09-10 | 2005-05-10 | International Business Machines Corporation | Method and structure for improved MOSFETs using poly/silicide gate height control |
| US7326609B2 (en) * | 2005-05-06 | 2008-02-05 | Chartered Semiconductor Manufacturing, Ltd. | Semiconductor device and fabrication method |
-
2004
- 2004-03-01 US US10/790,420 patent/US7064396B2/en not_active Expired - Lifetime
-
2005
- 2005-01-21 KR KR1020067017665A patent/KR101129070B1/ko not_active Expired - Fee Related
- 2005-01-21 EP EP05711765A patent/EP1776719A4/en not_active Withdrawn
- 2005-01-21 JP JP2007501778A patent/JP4777335B2/ja not_active Expired - Fee Related
- 2005-01-21 CN CN2005800068126A patent/CN1926693B/zh not_active Expired - Fee Related
- 2005-01-21 WO PCT/US2005/001916 patent/WO2005091758A2/en not_active Ceased
- 2005-02-17 TW TW094104676A patent/TWI367520B/zh not_active IP Right Cessation
- 2005-09-20 US US11/231,087 patent/US20060011988A1/en not_active Abandoned
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316302B1 (en) * | 1998-06-26 | 2001-11-13 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
| US6512273B1 (en) * | 2000-01-28 | 2003-01-28 | Advanced Micro Devices, Inc. | Method and structure for improving hot carrier immunity for devices with very shallow junctions |
| CN1449585A (zh) * | 2000-11-22 | 2003-10-15 | 株式会社日立制作所 | 半导体器件及其制造方法 |
| US20020164847A1 (en) * | 2001-05-04 | 2002-11-07 | Samsung Electronics Co., Ltd. | Method of forming a CMOS type semiconductor device |
| US6506642B1 (en) * | 2001-12-19 | 2003-01-14 | Advanced Micro Devices, Inc. | Removable spacer technique |
| US20030124864A1 (en) * | 2001-12-28 | 2003-07-03 | Hirofumi Komori | Semiconductor device and its manufacturing method |
| US20030181028A1 (en) * | 2002-03-19 | 2003-09-25 | Yeap Geoffrey C-F | Integrated circuit device and method therefor |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
Non-Patent Citations (2)
| Title |
|---|
| 说明书第2栏第25行-第5栏第19行、附图1-6. |
| 说明书第3栏第46行-第6栏第12行、附图1-2D. |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007525850A (ja) | 2007-09-06 |
| US20050190421A1 (en) | 2005-09-01 |
| CN1926693A (zh) | 2007-03-07 |
| TW200539259A (en) | 2005-12-01 |
| EP1776719A4 (en) | 2009-04-01 |
| EP1776719A2 (en) | 2007-04-25 |
| WO2005091758A2 (en) | 2005-10-06 |
| WO2005091758A3 (en) | 2006-01-26 |
| KR20060132920A (ko) | 2006-12-22 |
| TWI367520B (en) | 2012-07-01 |
| US7064396B2 (en) | 2006-06-20 |
| KR101129070B1 (ko) | 2012-03-26 |
| US20060011988A1 (en) | 2006-01-19 |
| JP4777335B2 (ja) | 2011-09-21 |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101020 Termination date: 20200121 |
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| CF01 | Termination of patent right due to non-payment of annual fee |