WO2005091758A2 - Integrated circuit with multiple spacer insulating region widths - Google Patents

Integrated circuit with multiple spacer insulating region widths Download PDF

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Publication number
WO2005091758A2
WO2005091758A2 PCT/US2005/001916 US2005001916W WO2005091758A2 WO 2005091758 A2 WO2005091758 A2 WO 2005091758A2 US 2005001916 W US2005001916 W US 2005001916W WO 2005091758 A2 WO2005091758 A2 WO 2005091758A2
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WO
WIPO (PCT)
Prior art keywords
region
gate
substrate
spacer
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/001916
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English (en)
French (fr)
Other versions
WO2005091758A3 (en
Inventor
Jian Chen
Vance H. Adams
Choh-Fei Yeap
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to KR1020067017665A priority Critical patent/KR101129070B1/ko
Priority to CN2005800068126A priority patent/CN1926693B/zh
Priority to EP05711765A priority patent/EP1776719A4/en
Priority to JP2007501778A priority patent/JP4777335B2/ja
Publication of WO2005091758A2 publication Critical patent/WO2005091758A2/en
Publication of WO2005091758A3 publication Critical patent/WO2005091758A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

  • This invention relates in general to integrated circuits.
  • Some integrated circuits utilize N-channel transistors and P-channel transistors having spacer insulating regions adjacent to the gates of these transistors.
  • the spacer insulating regions are the same width for both the N-channel transistors and the P-channel transistors.
  • the stress of the lattice of a transistor channel may affect performance of a P-channel transistor differently than that of an N-channel transistor.
  • increased compressive stress (or reduced tensile stress) on a channel lattice will improve the performance (e.g. improved drive current) of a P-channel transistor but decrease the performance of an N-channel transistor.
  • Figure 1 is a partial cross sectional view of one embodiment of a wafer during a stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 2 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 3 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 4 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 5 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 6 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 7 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 8 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of an integrated circuit according to the present invention.
  • Figure 9 is a cross sectional view of one embodiment of a transistor illustrating the effects of stress of the structures of the transistor.
  • Figures 1-8 show partial cross sectional views of one embodiment of various stages of a wafer in the manufacture of an integrated circuit having a P-channel transistor with an overall spacer insulating region width greater than that of an N-channel transistor. With some embodiments, this greater width may provide for a greater compressive channel stress or lesser tensile channel stress of the P-channel transistor than that for the N-channel transistor.
  • Figure 1 is a partial cross sectional view of a wafer 101 having an N-channel region 113 and a P-channel region 115.
  • wafer 101 includes a silicon layer 109 located on an insulative layer 107 (e.g. SiO 2 ).
  • the insulative layer 107 is located on a silicon substrate 105.
  • An isolation trench 111 is formed in layer 109 to isolate the N-channel region 113 from the P-channel region 115 in layer 109.
  • Layer 109 in P-channel region 115 is doped with an N-type conductivity dopant (N-type dopant) (e.g. arsenic, phosphorous), and layer 109 in the N-channel region is doped with a P-type conductivity dopant (P-type dopant) (e.g. boron, BF 2 ).
  • N-type dopant e.g. arsenic, phosphorous
  • P-type dopant e.g. boron, BF 2
  • Wafer 101 includes a gate dielectric 121 located on silicon layer 109 in N-channel region 113 and a gate dielectric 123 located on silicon layer 109 in P-channel region 115.
  • dielectrics 121 and 123 have the same thicknesses and were thermally grown from layer 109 after the formation of trench 111.
  • dielectrics 121 and 123 may have different thicknesses.
  • dielectrics 121 and 123 may be formed by different processes.
  • a gate 117 is formed on dielectric 121 in N-channel region 113 and a gate 119 is formed on dielectric 123 in P-channel region 115.
  • gates 117 and 119 are formed by depositing a layer (not shown) of polysilicon over wafer 101, doping the layer in the N-channel region 113, and then patterning the layer.
  • Wafer 101 may include other gates in other P-channel regions and N-channel regions not shown in the Figures. In other embodiments, the gates may be made of other materials, e.g. metal.
  • a thin sidewall spacer 125 is formed on gate 117 and a thin sidewall spacer 127 is formed on gate 119.
  • spacers 125 and 127 are formed by depositing a layer of silicon dioxide by chemical vapor deposition (CVD) followed by subsequent patterning.
  • CVD chemical vapor deposition
  • spacers 125 and 127 range in thickness from 60-150 angstroms. In other embodiments, spacers 125 and 127 may be formed by other methods, have other thicknesses, and/or be made of other materials.
  • dopants are implanted into layer 109 that will be later used to form source/drain extensions.
  • an N-type dopant e.g. arsenic, phosphorous
  • P-channel region 115 is masked.
  • halo implants of P-type dopants e.g. Boron, BF 2
  • the extension implants are vertical implants, but in other embodiments, may be angled implants. In some embodiments, the extension implants may include vertical implants followed by angled implants angled from the source side.
  • Regions 133 and 135 are doped with P-type dopants (e.g. boron, BF 2 ) by e.g. ion implantation while N-channel region 113 is masked.
  • P-type dopants e.g. boron, BF 2
  • halo implants of N-type dopants e.g. arsenic, phosphorous
  • the extension implants may be vertical and/or angled implants.
  • Figure 2 is a partial cross sectional side view of wafer 101 after a sidewall spacer 213 has been formed next to gate 117 and a sidewall spacer 217 has been formed next to gate 119.
  • a dielectric 211 e.g. CVD deposited silicon oxide
  • dielectric 211 has a thickness in the range of 60-200 angstroms (e.g. 80 angstroms).
  • Dielectric 211 is formed on spacers 125 and 127, which are not shown in Figure 2 (or in subsequent Figures).
  • a layer of spacer material (e.g. nitride, oxide, silicon oxynitride) is deposited on dielectric 211 (e.g. by a CVD type process).
  • the layer of spacer material may have a thickness ranging from 300 angstroms to 700 angstroms, but may be of other thicknesses in other embodiments.
  • Wafer 101 is then subjected to a dry etch that results in spacers 213 and 217 remaining from the layer of spacer material. During the dry etch, the thickness of the exposed portion of dielectric 211 is also reduced.
  • spacers 213 and 217 may be formed by other processes and/or be made of other materials.
  • spacers 213 and 217 may be made from other materials that are selectably etchable from the liners.
  • spacers 213 and 217 at their bases have a width in the range of 200-500 angstroms, but may be of other widths in other embodiments.
  • Figure 3 is a partial cross sectional side view of wafer 101 after sidewall spacer 321 has been formed adjacent to spacer 213 and sidewall spacer 327 has been formed adjacent to spacer 217.
  • a dielectric 319 e.g. CVD deposited silicon oxide
  • dielectric 319 has a thickness in the range of 60-200 angstroms.
  • a layer of spacer material e.g. nitride, oxide, silicon oxynitride
  • the wafer is then subjected to dry etch that results in spacers 321 and 327 remaining from the layer of spacer material.
  • spacers 321 and 327 may be formed by other methods and/or made by other materials. In some embodiments, spacers 321 and 327 at their bases have a width in the range of 200-500 angstroms, but may be of other widths in other embodiments.
  • a mask 403 is formed over N-channel region 113 to mask region 113.
  • mask 403 is formed of a patterned layer of photo resist.
  • Regions 407 and 409 of layer 109 are then, implanted with a P-type dopants (e.g. boron, BF 2 ) by ions 405.
  • a P-type dopants e.g. boron, BF 2
  • the ions are boron ions implanted at an energy of 5-10 KeV.
  • the dopant implanted into regions 409 and 407 will be utilized to form the deep source/drain regions of a P-channel transistor (transistor 823 in Figure 8) formed in P-channel region 115.
  • Ions 405 may be implanted vertically and/or at an angle.
  • mask 403 is removed and a mask 503 is formed over P-channel region 115.
  • Regions 511 and 509 of layer 109 are implanted with N-type dopants (e.g. arsenic, phosphorous) by ions 507.
  • the ions 507 are phosphorous ions implanted at an energy of 10-20 KeV.
  • the dopant implanted into regions 509 and 511 will be utilized to form the deep source/drain regions of an N-channel transistor (transistor 821 in Figure 8) formed in N-channel region 115.
  • Ions 507 may be implanted vertically and/or at an angle.
  • N-type dopants e.g. arsenic, phosphorous
  • ions 607 are utilized to improve the series resistance of the source/drain regions (e.g. 703 and 705 in Figure 8) of an N-channel transistor (821 in Figure 8) formed in region 113.
  • ions 607 are arsenic ions implanted at an energy in the range of 20-50 KeV. Ions 607 may be implanted vertically and/or at an angle.
  • ions 507 would be implanted after the removal of spacer 321 where the implanting of ions 607 would be omitted. In other embodiments, the implanting of ions 607 may be omitted.
  • the dopants in layer 109 are activated to form the source/drain regions of the transistors of regions 113 and 115.
  • the dopants in region 509, region 609, and region 129 are activated to form source/drain region 703.
  • the dopants in region 511, region 611, and region 131 are activated to form source/drain region 705.
  • the dopants of region 409 and region 133 are activated to form source/drain region 707, and the dopants of region 407 and region 135 are activated to form source/drain region 709.
  • the dopants are activated by rapid thermal annealing of wafer 101 at temperatures in the range of 1000 - 1100 C.
  • wafer 101 is subject to a wet etch to remove exposed remaining portions of dielectric 211 and dielectric 319.
  • silicide region 803 is formed in source/drain region 703, silicide region 805 is formed in source drain region 705, and silicide region 815 is formed in the top portion of gate 117.
  • Silicide region 807 is formed in source/drain region 707, silicide region 809 is formed in source/drain region 709, and silicide region 817 is formed in the top portion of gate 119.
  • these silicide regions are formed by depositing a metal layer (e.g. cobalt, nickel) over wafer 101 and reacting the metal layer with exposed silicon.
  • a metal layer e.g. cobalt, nickel
  • Wafer 101 may include other P-channel transistors with similar spacer insulating region widths and source/drain silicide region to gate distances as that shown and described for transistor 823. Wafer 101 may include other N-channel transistors with similar spacer insulating region widths and source/drain silicide region to gate distances as that shown and described for transistor 821.
  • wafer 101 In subsequent processes, other structures (not shown) are formed on wafer 101 including e.g. dielectrics, interconnects, and external terminals. The wafer is then signulated into multiple integrated circuits.
  • the distance between gate 117 and silicide region 803 is less than the distance between silicide region 807 and gate 119 due to the removal of spacer 321 (see Figure 6). Accordingly, the thickness of the spacer insulating region (e.g. sidewall spacer 213 and dielectric 211 in the embodiment shown) of N-type transistor 821 is less than the spacer insulating region (e.g. spacer 327, dielectric 319, spacer 217, and dielectric 211 in the embodiment shown) of P-channel transistor 823.
  • the increased width of the spacer insulating region (and increased distance between the source/drain silicide region and the gate) of P-channel transistor 823 acts to provide a relative increase in the compressive stress (or relative decrease in tensile stress) on the channel region of the P-channel transistor relative to the stress on the channel region of N-channel transistor 821.
  • This differential in stress may allow for performance improvement in one or both of the N-channel transistor and P-channel transistor over an integrated circuit having equal spacer insulting region widths for the N-channel and P-channel transistors.
  • the difference in spacer insulating region widths between the N-channel transistors and the P-channel may range from 50 angstroms to 1000 angstroms. However, other embodiments, the difference may be of other thicknesses.
  • FIG. 9 is a cross sectional side view of a transistor showing stresses on transistor structures and their effect on the channel region of the transistor.
  • Transistor 901 includes a spacer insulating region 907 adjacent to gate 903. Region 907 includes at least one spacer and may include one or more liners as well.
  • Silicide region 904 is formed in gate 903 and silicide regions 911 and 913 are located in substrate 902 adjacent to region 907.
  • spacer insulating region 907 includes at least one spacer that is tensile due to process induced stresses.
  • a silicon nitride film deposited by a low pressure CVD process may have an intrinsic tensile stress of 750 MPa. This tensile stress acts to provide a force to pull the spacer inward (see arrows 915 and 916). This inward force acts to provide a tensile stress on gate 903 (see arrows 917 and 918). This tensile stress on gate 903 provides a relatively compressive stress on channel 912 (see arrows 921 and 922).
  • spacer insulating region 907 provides more mass to the region, which may act to increase the tensile stress (as shown by arrows 917 and 918) on gate 903 and thereby increase the relative compressive stress (as shown by arrows 921 and 922) on channel region 912.
  • silicide regions 911 and 913 may be tensile due to thermal expansion mismatch between the suicides and the silicon of substrate 902. This tensile stress (as shown by arrows 927 and 928) acts to provide a tensile stress (as shown by arrows 930 and 931) on channel region 912.
  • Increasing the spacing between the source/drain silicide region and the channel region acts to reduce the relative tensile stress on the channel region due the stress of the source/drain silicide region.
  • providing a transistor with a greater spacer insulating region width and a greater distance from the source/drain silicide region and the channel region may provide a transistor with a relatively more compressed channel region, which may result in improved P-channel transistor performance.
  • providing a transistor with a smaller spacer insulating region width and a smaller distance from the source/drain silicide region and the channel region may provide a transistor with a relatively more tensile channel region, which may result in improved N-channel transistor performance.
  • the ability to differentiate the relative channel stress of the P-channel and N-channel transistors may be advantageous for circuits built in structures (e.g. a wafer with a silicon on insulator configuration) where transistor performance may be channel stress sensitive.
  • transistors with differences in spacer insulating widths and differences in the distance between the source/drain silicide region and gate may be made by other processes.
  • P-channel region 115 may be masked (e.g. with mask 503) prior to N-channel region 113 being masked (e.g. with mask 403) wherein spacer 321 would be removed prior to implanting ions 405.
  • the spacer insulating region may not include liners.
  • a difference in spacer insulating region widths and a difference between a source/drain silicide region and gate may be achieved by making spacers of different widths for the N-channel transistors and the P-channels transistors.
  • the thickness of the liner may affect channel stress.
  • the thinner the liner the more tensile the channel region.
  • reducing the thickness of dielectric 211 may increase tensile stress in the channel.
  • an integrated circuit includes a substrate, a first gate of an N-channel transistor over the substrate, a second gate of a P-channel transistor over the substrate, a first spacer insulating region adjacent to the first gate having a first width at its base, and a second spacer insulating region adjacent to the second gate having a second width at its base.
  • the second width is greater than the first width.
  • an integrated circuit in another embodiment, includes a substrate, a first gate of an N-channel transistor over the substrate, and a second gate of a P-channel transistor over the substrate.
  • the integrated circuit also includes a first silicide region in the substrate for the N-channel transistor.
  • the first silicide region is a first distance from the first gate.
  • the integrated circuit further includes a second silicide region in the substrate for the P-channel transistor.
  • the second silicide region is a second distance from the second gate. The second distance is greater than the first distance.
  • a method in another embodiment, includes providing a substrate and forming, over the substrate, a first gate for an N-channel transistor and a second gate for a P-channel transistor. The method also includes forming a first sidewall spacer for the N-channel transistor lateral to the first gate and a second sidewall spacer for the P-channel transistor lateral to the second gate and forming a third sidewall spacer for the N-channel transistor lateral to the first sidewall spacer and a fourth sidewall spacer for the P-channel transistor lateral to the second sidewall spacer.
  • the method further includes providing a first mask over the first gate and implanting dopants, while the first mask is over the first gate, of a first conductivity type into the substrate, removing the first mask after the implanting the dopants of the first conductivity type, and providing a second mask over the second gate.
  • the method further includes implanting dopants, while the second mask is over the second gate, of a second conductivity type into the substrate and removing the third sidewall spacer while the second mask is over the second gate.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
PCT/US2005/001916 2004-03-01 2005-01-21 Integrated circuit with multiple spacer insulating region widths Ceased WO2005091758A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020067017665A KR101129070B1 (ko) 2004-03-01 2005-01-21 스페이서 절연 영역 폭이 다른 집적 회로 및 그 제조 방법
CN2005800068126A CN1926693B (zh) 2004-03-01 2005-01-21 具有多种隔离体绝缘区宽度的集成电路
EP05711765A EP1776719A4 (en) 2004-03-01 2005-01-21 INTEGRATED CIRCUIT WITH MULTIPLE DISTANCE INSULATION WIDTHS
JP2007501778A JP4777335B2 (ja) 2004-03-01 2005-01-21 複合スペーサ絶縁領域幅を備えた集積回路の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/790,420 US7064396B2 (en) 2004-03-01 2004-03-01 Integrated circuit with multiple spacer insulating region widths
US10/790,420 2004-03-01

Publications (2)

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WO2005091758A2 true WO2005091758A2 (en) 2005-10-06
WO2005091758A3 WO2005091758A3 (en) 2006-01-26

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PCT/US2005/001916 Ceased WO2005091758A2 (en) 2004-03-01 2005-01-21 Integrated circuit with multiple spacer insulating region widths

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US (2) US7064396B2 (enExample)
EP (1) EP1776719A4 (enExample)
JP (1) JP4777335B2 (enExample)
KR (1) KR101129070B1 (enExample)
CN (1) CN1926693B (enExample)
TW (1) TWI367520B (enExample)
WO (1) WO2005091758A2 (enExample)

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US7064396B2 (en) 2006-06-20
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US20060011988A1 (en) 2006-01-19
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