US20070287275A1 - Method for fabricating doped polysilicon lines - Google Patents
Method for fabricating doped polysilicon lines Download PDFInfo
- Publication number
- US20070287275A1 US20070287275A1 US11/835,745 US83574507A US2007287275A1 US 20070287275 A1 US20070287275 A1 US 20070287275A1 US 83574507 A US83574507 A US 83574507A US 2007287275 A1 US2007287275 A1 US 2007287275A1
- Authority
- US
- United States
- Prior art keywords
- polysilicon layer
- polysilicon
- species
- atm
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 132
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000002019 doping agent Substances 0.000 claims abstract description 37
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 47
- 229910052757 nitrogen Inorganic materials 0.000 claims description 38
- 229910052698 phosphorus Inorganic materials 0.000 claims description 31
- 239000011574 phosphorus Substances 0.000 claims description 31
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 28
- 229910052785 arsenic Inorganic materials 0.000 claims description 14
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 70
- 238000009826 distribution Methods 0.000 description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 25
- 239000007943 implant Substances 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- -1 phosphorus ion Chemical class 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to the field of semiconductor fabrication; more specifically, it relates a method of fabricating doped polysilicon lines and complementary metal-oxide-silicon (CMOS) doped polysilicon gates.
- CMOS complementary metal-oxide-silicon
- Advanced CMOS devices utilize doped polysilicon lines and gates with metal silicide layers as a method of improving and matching the performance of N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs).
- NFETs N-channel field effect transistors
- PFETs P-channel field effect transistors
- controlling the width and sheet resistance of oppositely doped polysilicon lines and gates has become more important and difficult as the widths of polysilicon lines and gates have decreased. Therefore, there is a need for a method of fabricating doped polysilicon lines and gates with improved linewidth control.
- a first aspect of the present invention is a method of fabricating a semiconductor structure, forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
- FIGS. 1A through 1D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a first embodiment of the present invention
- FIGS. 2A through 2D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a second embodiment of the present invention
- FIGS. 3A through 3D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a third embodiment of the present invention.
- FIG. 4 is a plot of concentration of implanted species versus distance from a top surface of a doped polysilicon layer according to the present invention
- FIGS. 5A and 5B are partial cross-sectional views illustrating common intermediate steps for fabricating doped polysilicon lines and gates according to the present invention
- FIG. 6 is a partial cross-sectional view of a problem solved by the present invention.
- FIGS. 7A through 7E are partial cross-sectional views illustrating common last steps for fabricating doped polysilicon lines and gates according to the present invention.
- a doped polysilicon gate should be considered a doped polysilicon line used for a specific purpose.
- FIGS. 1A through 1D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a first embodiment of the present invention.
- formed in a silicon substrate 100 are an N-well 105 , a P-well 110 and shallow trench isolation (STI) 115 .
- STI 115 may be formed by etching a trench into substrate 100 , depositing a dielectric layer on a surface 120 of the substrate of sufficient thickness to fill the trench, and then performing a chemical-mechanical-polishing step to remove excess dielectric layer.
- formation of STI 115 is optional, and STI 115 need not be present.
- Formed on top surface 120 of substrate 100 is a gate dielectric layer 125 .
- gate dielectric layer 125 Formed on a top surface 130 of gate dielectric layer 125 is a polysilicon layer 135 .
- gate dielectric layer 125 is thermal silicon oxide having a thickness of between about 0.8 nm to about 4 nm.
- polysilicon layer 135 is undoped polysilicon having a thickness of between about 40 nm to about 200 nm.
- a photoresist layer 140 is formed on a top surface 145 of polysilicon layer 135 .
- Photoresist layer 140 is then removed from over P-well 110 by one of by one of any number of photolithographic methods known in the art.
- a phosphorus ion implantation is performed.
- Photoresist layer 140 is of sufficient thickness to about block phosphorus ion implantation into polysilicon layer 135 over N-well 105 .
- the ion implantation is performed to place the peak (the maximum) of the implanted phosphorus distribution concentration (in atm/cm 3 ) proximate to top surface 145 of polysilicon layer 135 .
- Proximate is defined herein as within about 0 nm to about a value of one fourth of the thickness of polysilicon layer 135 . (See also FIG. 4 , distances D 1 A and D 1 B).
- the ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110 .
- the phosphorus ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- phosphorus is implanted at a dose of about 5E14 atm/cm 2 to about 5E16 atm/cm 2 at an energy of about 30 KeV or less.
- Arsenic may be substituted for phosphorus and the arsenic.
- arsenic is implanted at a dose of about 5E14 atm/cm 2 to about 5E16 atm/cm 2 at an energy of about 60 KeV or less.
- Photoresist layer 140 is then removed.
- the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness of polysilicon layer 135 .
- a photoresist layer 150 is formed on top surface 145 of polysilicon layer 135 .
- Photoresist layer 150 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art.
- a boron ion implantation is performed.
- Photoresist layer 150 is of sufficient thickness to about block boron ion implantation into polysilicon layer 135 over P-well 110 .
- the ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105 .
- Photoresist layer 150 is then removed.
- a nitrogen containing species ion implantation is performed.
- the ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration of implanted nitrogen penetrating into either gate dielectric layer 125 , N-well 105 and P-well 110 is not significant.
- the nitrogen ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- nitrogen is implanted at a dose of about 1E14 atm/cm 2 to about 4E15 atm/cm 2 at an energy of about 20 KeV or less.
- suitable nitrogen species include but is not limited to N, N 2 , NO, NF 3 , N 2 O and NH 3 .
- the nitrogen dose and energy should be scaled proportionally to the thickness of polysilicon layer 135 . The steps illustrated in FIGS. 5A and 5B are next performed.
- one intent of the phosphorus (or arsenic), boron and nitrogen containing species ion implantations is to keep a maximum amount as possible of implanted species contained within the polysilicon layer at the time of ion implantation as well as after various later heat cycles and to keep a minimum amount as possible of implanted species from penetrating through the polysilicon layer into the underlying layers or into the substrate.
- the ion implantations are shallow (low energy) with concentration peaks close to the surface of the polysilicon and concentration tails that fall off to very low concentrations while still within the polysilicon.
- the implanted species is essentially contained within the polysilicon layer.
- FIGS. 2A through 2D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a second embodiment of the present invention.
- FIG. 2A is identical to FIG. 1A .
- a nitrogen containing species ion implantation is performed. The ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate to top surface 145 of polysilicon layer 135 . The ion implantation is further performed so that the concentration of implanted nitrogen penetrating into either gate dielectric layer 125 , N-well 105 and P-well 110 is not significant.
- the nitrogen ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- nitrogen is implanted at a dose of about 1E14 atm/cm 2 to about 4E14 atm/cm 2 at an energy of about 20 KeV or less.
- suitable nitrogen species include but is not limited to N 2 , NO, NF 3 , N 2 O and NH 3 .
- the nitrogen dose and energy should be scaled proportionally to the thickness of polysilicon layer 135 .
- a photoresist layer 155 is formed on top surface 145 of polysilicon layer 135 .
- Photoresist layer 155 is then removed from over P-well 110 by one of any number of photolithographic methods known in the art. Then a phosphorus ion implantation is performed.
- Photoresist layer 155 is of sufficient thickness to about block phosphorus ion implantation into polysilicon layer 135 over N-well 105 . The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110 .
- the phosphorus ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- phosphorus is implanted at a dose of about 5E14 atm/cm 2 to about 5E16 atm/cm 2 at an energy of about 30 KeV or less.
- Arsenic may be substituted for phosphorus.
- arsenic is implanted at a dose of about 5E14 atm/cm 2 to about 5E 16 atm/cm 2 at an energy of about 60 KeV or less.
- the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness of polysilicon layer 135 .
- Photoresist layer 155 is then removed.
- a photoresist layer 160 is formed on top surface 145 of polysilicon layer 135 .
- Photoresist layer 160 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art.
- a boron ion implantation is performed.
- Photoresist layer 160 is of sufficient thickness to about block boron ion implantation into polysilicon layer 135 over P-well 110 .
- the ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105 .
- Photoresist layer 160 is then removed. The steps illustrated in FIGS. 5A and 5B are next performed.
- FIGS. 3A through 3D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a third embodiment of the present invention.
- FIG. 3A is identical to FIG. 1A .
- a photoresist layer 165 is formed on top surface 145 of polysilicon layer 135 .
- Photoresist layer 165 is then removed from over P-well 110 by one of any number of photolithographic methods known in the art. Then a phosphorus ion implantation is performed.
- Photoresist layer 165 is of sufficient thickness to about block phosphorus ion implantation into polysilicon layer 135 over N-well 105 .
- the ion implantation is performed to place the peak of the implanted phosphorus distribution concentration proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110 .
- the phosphorus ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- phosphorus is implanted at a dose of about 5E14 atm/cm 2 to about 5E16 atm/cm 2 at an energy of about 30 KeV or less.
- Arsenic may be substituted for phosphorus.
- arsenic is implanted at a dose of about 5E 14 atm/cm 2 to about 5E16 atm/cm 2 at an energy of about 60 KeV or less.
- the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness of polysilicon layer 135 .
- Photoresist layer 165 is of sufficient thickness to about block nitrogen species ion implantation into polysilicon layer 135 over N-well 105 .
- the ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration of implanted nitrogen penetrating into either gate dielectric layer 125 and P-well 110 is not significant.
- the nitrogen ion implant concentration distribution profile is illustrated in FIG. 4 and described infra.
- nitrogen is implanted at a dose of about 1E14 atm/cm 2 to about 4E15 atm/cm 2 at an energy of about 20 KeV or less.
- the nitrogen dose and energy should be scaled proportionally to the thickness of polysilicon layer 135 .
- suitable nitrogen species include but is not limited to N 2 , NO, NF 3 , N 2 O and NH 3 .
- Photoresist layer 165 is then removed.
- a photoresist layer 170 is formed on top surface 145 of polysilicon layer 135 .
- Photoresist layer 170 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art.
- a boron ion implantation is performed.
- Photoresist layer 170 is of sufficient thickness to about block boron ion implantation into polysilicon layer 135 over P-well 110 .
- the ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate to top surface 145 of polysilicon layer 135 .
- the ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105 .
- Photoresist layer 170 is then removed. The steps illustrated in FIGS. 5A and 5B are next performed.
- the present invention may be practiced by (1) fully matching ion implantation concentration profiles (concentration vs. ion implanted distance) of N-dopant (i.e. phosphorus or arsenic) and nitrogen species at the same distance into the polysilicon, by (2) matching ion implantation concentration profiles of N-dopant and nitrogen species, within a predetermined concentration range, at the same distances into the polysilicon, by (3) matching, within a predetermined concentration range, the surface concentrations of N-dopant and nitrogen in the polysilicon, or by (4) by matching, within a predetermined concentration range, peak concentrations of N-dopant and nitrogen at the same distance into the polysilicon.
- N-dopant i.e. phosphorus or arsenic
- FIG. 4 is a plot of concentration of implanted species versus distance from a top surface of a doped polysilicon layer according to the present invention.
- curve 175 N-dopant
- 180 nitrogen species
- option (2) matching ion implantation concentration profiles of N-dopant and nitrogen species, within a predetermined concentration range, at the same distances into the polysilicon. That is, an equation defining curve 175 and an equation defining curve 180 would yield, for the same distance from the top surface of the polysilicon, a concentration of implanted species within predetermined range of concentration of each other. In a full ion implantation profiles match, option (1) curves 175 and 180 would overlay.
- the N-dopant (phosphorus or arsenic) ion implantation concentration distribution profile is indicated by curve 175 and the nitrogen species ion implantation concentration distribution profile is indicated by curve 180 . While curve 180 is illustrated above curve 175 , curve 175 could be above 180 . Also curve 175 and curve 180 could cross at one or more points. The exact relationship between curves 175 and 180 is determined by the specific ion implant dose and energy or the N dopant and the specific ion implant dose and energy or the nitrogen. The surface distribution concentration C 2 A of curve 175 and C 2 B of curve 180 occur respectively at distance 0 into the polysilicon layer.
- C 2 A is between about 1E18 atm/cm 3 and about 1E21 atm/cm 3 and concentration C 2 B is about 1E18 atm/cm 3 and about 1E22 atm/cm 3 .
- the ranges of values for C 2 A and C 2 B may overlap.
- the peak distribution concentration C 3 A of curve 175 and C 3 B of curve 180 occur respectively proximate to the surface of the polysilicon at distance D 1 A and D 1 B into the polysilicon layer.
- C 3 A is between about 1E18 atm/cm 3 and about 1E22 atm/cm 3 and concentration C 3 B is about 1E18 atm/cm 3 and about 1E21 atm/cm 3 .
- the ranges of values for C 3 A and C 3 B may overlap.
- D 1 A is between about 0 nm and about 1 ⁇ 3 the thickness of the polysilicon and depth D 1 B is about 0 nm to about 2 ⁇ 3 the thickness of the polysilicon.
- the ranges for values for D 1 A and D 1 B may overlap.
- a concentration C 1 is defined in FIG. 4 for curve 175 at a distance D 2 A and for curve 180 at a distance D 2 B into the polysilicon layer.
- D 2 A is between about 10 nm and the thickness of the polysilicon and D 2 B is between about 50% and about 150% of D 2 A.
- Concentration C 1 is a concentration at which an insignificant amount to none of the ion implanted species exists hence essentially the implanted N dopant species and implanted nitrogen containing species are contained with the polysilicon layer.
- An insignificant amount of implanted species is defined as an amount of implanted species, that if present, would not significantly effect chemical processes or electrical parameters of the polysilicon layer (or gate dielectric layer or P-well) in which the implanted species is present.
- the gate dielectric layer occurs between a distance D 3 and D 4 .
- Distance D 3 is the same as the thickness of the polysilicon layer discussed supra in reference to FIG. 1A and (D 4 -D 3 ) is the thickness of the gate dielectric layer discussed supra in reference to FIG. 1A .
- FIGS. 5A and 5B are partial cross-sectional views illustrating common intermediate steps for fabricating doped polysilicon lines and gates according to the present invention.
- polysilicon layer 135 (see FIG. 1D, 2D or 3 D ⁇ is etched into gate electrodes 185 A and 185 B. Formation of gate electrodes 185 A and 185 B may be accomplished by one of any number of plasma etch processes selective to etch polysilicon over oxide well known in the art.
- an oxidation is performed to simultaneously grow a thermal oxide layer 190 A over sidewalls 195 A and a top surface 200 A of gate electrode 185 A and a thermal oxide layer 190 B over sidewalls 195 B and a top surface 200 B of gate electrode 185 B.
- the width of gate electrode 185 A at top surface 200 A and the width of gate electrode 185 B at top surface 200 B are both about equal to W 1 .
- Gate electrode 185 A is doped P type and gate electrode 185 B is doped N type.
- Gate electrode 185 B (and possibly gate electrode 185 A depending upon which embodiment of the present invention is used prior to the thermal oxidation step) has also been nitrogenated by the nitrogen ion species ion implantation described supra.
- the thermal oxidation rate of N-doped polysilicon is retarded to be about the same as the thermal oxidation rate of P-doped polysilicon.
- An example of a thermal oxidation is a furnace oxidation performed for in about a 97% O 2 and about 3% HCL generating gas a temperature of about 750° C. for 35 minutes which will grow about 40 angstroms of Si)2 on ⁇ 100> single-crystal silicon. The steps illustrated in FIGS. 7A through 7E are next performed.
- FIG. 6 is a partial cross-sectional view of a problem solved by the present invention.
- gate electrode 190 C has a width W 2 at a top surface 200 C (where W 2 is less than W 1 ) because N-doped polysilicon oxidizes at a faster rate than P-doped polysilicon.
- W 2 is less than W 1
- Table II illustrates the effect of nitrogen species ion implantation: TABLE II Thermal Oxide Thickness Polysilicon Width at Top Nitrogen Implant N-doped P-doped N-doped P-doped Energy and Dose Polysilicon Polysilicon Polysilicon Polysilicon Polysilicon NONE 149 ⁇ 61 ⁇ 13 nm 28 nm 6.3 KeV, 5E15 atm/cm 2 64 ⁇ 58 ⁇ 23 nm 27 nm 6.3 KeV, 1E16 atm/cm 2 52 ⁇ 58 ⁇ 23 nm 30 nm
- FIGS. 7A through 7E are partial cross-sectional views illustrating common last steps for fabricating doped polysilicon lines and gates according to the present invention.
- FIG. 7A is identical to FIG. 5B .
- dielectric spacers 205 A and 205 B are formed over thermal oxide layers 190 A and 190 B on sidewalls 195 A and 195 B of gate electrodes 185 A and 185 B respectively.
- Spacers 205 A and 205 B may be formed by deposition of a conformal material (for example, silicon nitride) followed by a reactive ion etch (RIE) to remove the conformal material from surfaces perpendicular to the direction of the ion flux.
- RIE reactive ion etch
- extension and/or halo and source drain ion implants are performed to P+ source drains 210 in N-well 105 and N+ source drains 215 in P-well 115 . Additional spacers may be formed between various extension, halo and source/drain ion implants.
- gate dielectric layer 125 is removed wherever the gate dielectric layer is not protected by gate electrodes 185 A and 185 B and by spacers 105 A and 205 B. (The gate dielectric on the sidewalls of the gate electrodes also protects the underlying gate dielectric layer.) Also, thermal oxide layer 190 A and 190 B on top surfaces 200 A and 200 B of gate electrodes 185 A and 185 B respectively is removed. Gate dielectric layer 125 and thermal oxide layer 190 A and 190 B removal may be accomplished, for example, using a dilute aqueous HF containing solution.
- a metal layer 220 is deposited.
- Metal layer 220 may be nickel, titanium, platinum or cobalt.
- FIG. 7E a portion of metal layer 220 in contact with gate electrodes 185 A and 185 B and with P+ source drains 210 and N+ source/drains 215 is converted to a metal silicide 225 by annealing and removing unreacted metal layer 220 by methods well known in the art. Fabrication of a PFET 230 and an NFET 235 having similar gate electrode linewidths and resistivity is now complete.
- the present invention provides a method of fabricating doped polysilicon lines and gates with improved linewidth control.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
Description
- This application is a division of U.S. patent application Ser. No. 10/711,771 filed on Oct. 4, 2004.
- The present invention relates to the field of semiconductor fabrication; more specifically, it relates a method of fabricating doped polysilicon lines and complementary metal-oxide-silicon (CMOS) doped polysilicon gates.
- Advanced CMOS devices utilize doped polysilicon lines and gates with metal silicide layers as a method of improving and matching the performance of N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs). However, controlling the width and sheet resistance of oppositely doped polysilicon lines and gates has become more important and difficult as the widths of polysilicon lines and gates have decreased. Therefore, there is a need for a method of fabricating doped polysilicon lines and gates with improved linewidth control.
- A first aspect of the present invention is a method of fabricating a semiconductor structure, forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
- The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
-
FIGS. 1A through 1D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a first embodiment of the present invention; -
FIGS. 2A through 2D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a second embodiment of the present invention; -
FIGS. 3A through 3D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a third embodiment of the present invention; -
FIG. 4 is a plot of concentration of implanted species versus distance from a top surface of a doped polysilicon layer according to the present invention; -
FIGS. 5A and 5B are partial cross-sectional views illustrating common intermediate steps for fabricating doped polysilicon lines and gates according to the present invention; -
FIG. 6 is a partial cross-sectional view of a problem solved by the present invention; and -
FIGS. 7A through 7E are partial cross-sectional views illustrating common last steps for fabricating doped polysilicon lines and gates according to the present invention. - The present invention will be described using fabrication of doped polysilicon gates as exemplary of the fabrication process of the present invention. A doped polysilicon gate should be considered a doped polysilicon line used for a specific purpose.
-
FIGS. 1A through 1D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a first embodiment of the present invention. InFIG. 1A , formed in asilicon substrate 100 are an N-well 105, a P-well 110 and shallow trench isolation (STI) 115. STI 115 may be formed by etching a trench intosubstrate 100, depositing a dielectric layer on asurface 120 of the substrate of sufficient thickness to fill the trench, and then performing a chemical-mechanical-polishing step to remove excess dielectric layer. However, formation ofSTI 115 is optional, and STI 115 need not be present. Formed ontop surface 120 ofsubstrate 100 is a gatedielectric layer 125. Formed on atop surface 130 of gatedielectric layer 125 is apolysilicon layer 135. In one example, gatedielectric layer 125 is thermal silicon oxide having a thickness of between about 0.8 nm to about 4 nm. In one example,polysilicon layer 135 is undoped polysilicon having a thickness of between about 40 nm to about 200 nm. - In
FIG. 1B , aphotoresist layer 140 is formed on atop surface 145 ofpolysilicon layer 135.Photoresist layer 140 is then removed from over P-well 110 by one of by one of any number of photolithographic methods known in the art. Then a phosphorus ion implantation is performed.Photoresist layer 140 is of sufficient thickness to about block phosphorus ion implantation intopolysilicon layer 135 over N-well 105. The ion implantation is performed to place the peak (the maximum) of the implanted phosphorus distribution concentration (in atm/cm3) proximate totop surface 145 ofpolysilicon layer 135. Proximate is defined herein as within about 0 nm to about a value of one fourth of the thickness ofpolysilicon layer 135. (See alsoFIG. 4 , distances D1A and D1B). The ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110. The phosphorus ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, phosphorus is implanted at a dose of about 5E14 atm/cm2 to about 5E16 atm/cm2 at an energy of about 30 KeV or less. Arsenic may be substituted for phosphorus and the arsenic. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, arsenic is implanted at a dose of about 5E14 atm/cm2 to about 5E16 atm/cm2 at an energy of about 60 KeV or less.Photoresist layer 140 is then removed. In other examples, the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness ofpolysilicon layer 135. - In
FIG. 1C , aphotoresist layer 150 is formed ontop surface 145 ofpolysilicon layer 135.Photoresist layer 150 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art. Then a boron ion implantation is performed.Photoresist layer 150 is of sufficient thickness to about block boron ion implantation intopolysilicon layer 135 over P-well 110. The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105.Photoresist layer 150 is then removed. - In
FIG. 1D , a nitrogen containing species ion implantation is performed. The ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration of implanted nitrogen penetrating into eithergate dielectric layer 125, N-well 105 and P-well 110 is not significant. The nitrogen ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, nitrogen (as N) is implanted at a dose of about 1E14 atm/cm2 to about 4E15 atm/cm2 at an energy of about 20 KeV or less. Other suitable nitrogen species include but is not limited to N, N2, NO, NF3, N2O and NH3. In other examples, the nitrogen dose and energy should be scaled proportionally to the thickness ofpolysilicon layer 135. The steps illustrated inFIGS. 5A and 5B are next performed. - For the first, as well as the second and third embodiments of the present invention, one intent of the phosphorus (or arsenic), boron and nitrogen containing species ion implantations is to keep a maximum amount as possible of implanted species contained within the polysilicon layer at the time of ion implantation as well as after various later heat cycles and to keep a minimum amount as possible of implanted species from penetrating through the polysilicon layer into the underlying layers or into the substrate. Thus, the ion implantations are shallow (low energy) with concentration peaks close to the surface of the polysilicon and concentration tails that fall off to very low concentrations while still within the polysilicon. Thus the implanted species is essentially contained within the polysilicon layer. Less than about 2E12 atm/cm2 of any of the ion implanted species is intended to penetrate into substrate in the case of a polysilicon line or into the gate dielectric layer or N-well or P-well in the gate of polysilicon gates.
-
FIGS. 2A through 2D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a second embodiment of the present invention.FIG. 2A is identical toFIG. 1A . InFIG. 2B , a nitrogen containing species ion implantation is performed. The ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration of implanted nitrogen penetrating into eithergate dielectric layer 125, N-well 105 and P-well 110 is not significant. The nitrogen ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, nitrogen (as N) is implanted at a dose of about 1E14 atm/cm2 to about 4E14 atm/cm2 at an energy of about 20 KeV or less. Other suitable nitrogen species include but is not limited to N2, NO, NF3, N2O and NH3. In other examples, the nitrogen dose and energy should be scaled proportionally to the thickness ofpolysilicon layer 135. - In
FIG. 2C , aphotoresist layer 155 is formed ontop surface 145 ofpolysilicon layer 135.Photoresist layer 155 is then removed from over P-well 110 by one of any number of photolithographic methods known in the art. Then a phosphorus ion implantation is performed.Photoresist layer 155 is of sufficient thickness to about block phosphorus ion implantation intopolysilicon layer 135 over N-well 105. The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110. The phosphorus ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, phosphorus is implanted at a dose of about 5E14 atm/cm2 to about 5E16 atm/cm2 at an energy of about 30 KeV or less. Arsenic may be substituted for phosphorus. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, arsenic is implanted at a dose of about 5E14 atm/cm2 to about 5E 16 atm/cm2 at an energy of about 60 KeV or less. In other examples, the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness ofpolysilicon layer 135.Photoresist layer 155 is then removed. - In
FIG. 2D , aphotoresist layer 160 is formed ontop surface 145 ofpolysilicon layer 135.Photoresist layer 160 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art. Then a boron ion implantation is performed.Photoresist layer 160 is of sufficient thickness to about block boron ion implantation intopolysilicon layer 135 over P-well 110. The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105.Photoresist layer 160 is then removed. The steps illustrated inFIGS. 5A and 5B are next performed. -
FIGS. 3A through 3D are partial cross-sectional views illustrating initial steps for fabricating doped polysilicon lines and gates according to a third embodiment of the present invention.FIG. 3A is identical toFIG. 1A . InFIG. 3B , aphotoresist layer 165 is formed ontop surface 145 ofpolysilicon layer 135.Photoresist layer 165 is then removed from over P-well 110 by one of any number of photolithographic methods known in the art. Then a phosphorus ion implantation is performed.Photoresist layer 165 is of sufficient thickness to about block phosphorus ion implantation intopolysilicon layer 135 over N-well 105. The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration distribution profile of implanted phosphorus is such as to not significantly affect the overall P dopant level of P-well 110. The phosphorus ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, phosphorus is implanted at a dose of about 5E14 atm/cm2 to about 5E16 atm/cm2 at an energy of about 30 KeV or less. Arsenic may be substituted for phosphorus. In one example, withpolysilicon layer 135 having a thickness of about 0.15 nm, arsenic is implanted at a dose of about 5E 14 atm/cm2 to about 5E16 atm/cm2 at an energy of about 60 KeV or less. In other examples, the phosphorus and arsenic doses and energies should be scaled proportionally to the thickness ofpolysilicon layer 135. - In
FIG. 3C , a nitrogen containing species ion implantation is performed.Photoresist layer 165 is of sufficient thickness to about block nitrogen species ion implantation intopolysilicon layer 135 over N-well 105. The ion implantation is performed to place the peak of the implanted nitrogen species distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration of implanted nitrogen penetrating into eithergate dielectric layer 125 and P-well 110 is not significant. The nitrogen ion implant concentration distribution profile is illustrated inFIG. 4 and described infra. In one example, nitrogen (as N) is implanted at a dose of about 1E14 atm/cm2 to about 4E15 atm/cm2 at an energy of about 20 KeV or less. In other examples, the nitrogen dose and energy should be scaled proportionally to the thickness ofpolysilicon layer 135. Other suitable nitrogen species include but is not limited to N2, NO, NF3, N2O and NH3.Photoresist layer 165 is then removed. - In
FIG. 3D , aphotoresist layer 170 is formed ontop surface 145 ofpolysilicon layer 135.Photoresist layer 170 is then removed from over N-well 105 by one of any number of photolithographic methods known in the art. Then a boron ion implantation is performed.Photoresist layer 170 is of sufficient thickness to about block boron ion implantation intopolysilicon layer 135 over P-well 110. The ion implantation is performed to place the peak of the implanted phosphorus distribution concentration profile proximate totop surface 145 ofpolysilicon layer 135. The ion implantation is further performed so that the concentration distribution profile of implanted boron is such as to not significantly affect the overall N dopant level of N-well 105.Photoresist layer 170 is then removed. The steps illustrated inFIGS. 5A and 5B are next performed. - The present invention may be practiced by (1) fully matching ion implantation concentration profiles (concentration vs. ion implanted distance) of N-dopant (i.e. phosphorus or arsenic) and nitrogen species at the same distance into the polysilicon, by (2) matching ion implantation concentration profiles of N-dopant and nitrogen species, within a predetermined concentration range, at the same distances into the polysilicon, by (3) matching, within a predetermined concentration range, the surface concentrations of N-dopant and nitrogen in the polysilicon, or by (4) by matching, within a predetermined concentration range, peak concentrations of N-dopant and nitrogen at the same distance into the polysilicon.
-
FIG. 4 is a plot of concentration of implanted species versus distance from a top surface of a doped polysilicon layer according to the present invention. InFIG. 4 , curve 175 (N-dopant) and 180 (nitrogen species) are illustrated using option (2), matching ion implantation concentration profiles of N-dopant and nitrogen species, within a predetermined concentration range, at the same distances into the polysilicon. That is, anequation defining curve 175 and anequation defining curve 180 would yield, for the same distance from the top surface of the polysilicon, a concentration of implanted species within predetermined range of concentration of each other. In a full ion implantation profiles match, option (1) curves 175 and 180 would overlay. - In
FIG. 4 , the N-dopant (phosphorus or arsenic) ion implantation concentration distribution profile is indicated bycurve 175 and the nitrogen species ion implantation concentration distribution profile is indicated bycurve 180. Whilecurve 180 is illustrated abovecurve 175,curve 175 could be above 180. Alsocurve 175 andcurve 180 could cross at one or more points. The exact relationship betweencurves curve 175 and C2B ofcurve 180 occur respectively atdistance 0 into the polysilicon layer. In one example, C2A is between about 1E18 atm/cm3 and about 1E21 atm/cm3 and concentration C2B is about 1E18 atm/cm3 and about 1E22 atm/cm3. The ranges of values for C2A and C2B may overlap. - The peak distribution concentration C3A of
curve 175 and C3B ofcurve 180 occur respectively proximate to the surface of the polysilicon at distance D1A and D1B into the polysilicon layer. In one example, C3A is between about 1E18 atm/cm3 and about 1E22 atm/cm3 and concentration C3B is about 1E18 atm/cm3 and about 1E21 atm/cm3. The ranges of values for C3A and C3B may overlap. - In one example D1A is between about 0 nm and about ⅓ the thickness of the polysilicon and depth D1B is about 0 nm to about ⅔ the thickness of the polysilicon. The ranges for values for D1A and D1B may overlap.
- A concentration C1 is defined in
FIG. 4 forcurve 175 at a distance D2A and forcurve 180 at a distance D2B into the polysilicon layer. D2A is between about 10 nm and the thickness of the polysilicon and D2B is between about 50% and about 150% of D2A. Concentration C1 is a concentration at which an insignificant amount to none of the ion implanted species exists hence essentially the implanted N dopant species and implanted nitrogen containing species are contained with the polysilicon layer. An insignificant amount of implanted species is defined as an amount of implanted species, that if present, would not significantly effect chemical processes or electrical parameters of the polysilicon layer (or gate dielectric layer or P-well) in which the implanted species is present. - Table I summarizes the relationship between curve 175 (N Dopant) and curve 180 (Nitrogen species).
TABLE I Minimum Maximum Value Value N Dopant Surface Concentration (C2A) about 1E18 atm/cm3 about 1E22 atm/cm3 Nitrogen Species Surface about 1E18 atm/cm3 about 1E21 atm/cm3 Concentration(C2B— N Dopant Peak Concentration (C3A) about 1E18 atm/cm3 about 1E22 atm/cm3 Nitrogen Species Peak about 1E18 atm/cm3 about 1E22 atm/cm3 Concentration(C3B) N Dopant Peak Depth (D1A) about 0 nm about equal to ⅓ the polysilicon thickness Nitrogen Species Peak Depth (D1B) about 0 nm about equal to ⅔ the polysilicon thickness N Dopant and Nitrogen Species Not Applicable about 1E15 atm/cm3 Insignificant Concentration (C1) N Dopant Insignificant Concentration 10 nm about equal to the full Depth (D2A) thickness of the polysilicon Nitrogen Species Insignificant about 150% of D1A about 150% of D2A Concentration Depth (D2B) - Also in
FIG. 4 , the gate dielectric layer occurs between a distance D3 and D4. Distance D3 is the same as the thickness of the polysilicon layer discussed supra in reference toFIG. 1A and (D4-D3) is the thickness of the gate dielectric layer discussed supra in reference toFIG. 1A . -
FIGS. 5A and 5B are partial cross-sectional views illustrating common intermediate steps for fabricating doped polysilicon lines and gates according to the present invention. InFIG. 5A , polysilicon layer 135 (seeFIG. 1D, 2D or 3D} is etched intogate electrodes gate electrodes - In
FIG. 5B , an oxidation is performed to simultaneously grow athermal oxide layer 190A oversidewalls 195A and atop surface 200A ofgate electrode 185A and athermal oxide layer 190B oversidewalls 195B and atop surface 200B ofgate electrode 185B. The width ofgate electrode 185A attop surface 200A and the width ofgate electrode 185B attop surface 200B are both about equal to W1.Gate electrode 185A is doped P type andgate electrode 185B is doped N type.Gate electrode 185B (and possiblygate electrode 185A depending upon which embodiment of the present invention is used prior to the thermal oxidation step) has also been nitrogenated by the nitrogen ion species ion implantation described supra. This reduces (retards) the thermal oxidation rate of N-doped polysilicon. In one example, the thermal oxidation rate of N-doped polysilicon is retarded to be about the same as the thermal oxidation rate of P-doped polysilicon. An example of a thermal oxidation is a furnace oxidation performed for in about a 97% O2 and about 3% HCL generating gas a temperature of about 750° C. for 35 minutes which will grow about 40 angstroms of Si)2 on <100> single-crystal silicon. The steps illustrated inFIGS. 7A through 7E are next performed. -
FIG. 6 is a partial cross-sectional view of a problem solved by the present invention. InFIG. 6 , the situation that would otherwise prevail if the nitrogen species ion implantation had not been performed. After thermal oxidation,gate electrode 190C has a width W2 at atop surface 200C (where W2 is less than W1) because N-doped polysilicon oxidizes at a faster rate than P-doped polysilicon. The situation wherein the N-dopant concentration is higher near atop surface 200C ofgate electrode 185C is illustrated. - Table II illustrates the effect of nitrogen species ion implantation:
TABLE II Thermal Oxide Thickness Polysilicon Width at Top Nitrogen Implant N-doped P-doped N-doped P-doped Energy and Dose Polysilicon Polysilicon Polysilicon Polysilicon NONE 149 Å 61 Å 13 nm 28 nm 6.3 KeV, 5E15 atm/cm2 64 Å 58 Å 23 nm 27 nm 6.3 KeV, 1E16 atm/cm2 52 Å 58 Å 23 nm 30 nm -
FIGS. 7A through 7E are partial cross-sectional views illustrating common last steps for fabricating doped polysilicon lines and gates according to the present invention.FIG. 7A is identical toFIG. 5B . InFIG. 7B ,dielectric spacers thermal oxide layers sidewalls gate electrodes Spacers - In
FIG. 7C ,gate dielectric layer 125 is removed wherever the gate dielectric layer is not protected bygate electrodes spacers 105A and 205B. (The gate dielectric on the sidewalls of the gate electrodes also protects the underlying gate dielectric layer.) Also,thermal oxide layer top surfaces gate electrodes Gate dielectric layer 125 andthermal oxide layer - In
FIG. 7D ametal layer 220 is deposited.Metal layer 220 may be nickel, titanium, platinum or cobalt. InFIG. 7E , a portion ofmetal layer 220 in contact withgate electrodes metal silicide 225 by annealing and removingunreacted metal layer 220 by methods well known in the art. Fabrication of aPFET 230 and anNFET 235 having similar gate electrode linewidths and resistivity is now complete. - Thus, the present invention provides a method of fabricating doped polysilicon lines and gates with improved linewidth control.
- The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims (11)
1. A method of fabricating a semiconductor structure, comprising:
forming a dielectric layer on a top surface of a substrate;
forming a polysilicon layer on a top surface of said dielectric layer;
implanting said polysilicon layer with N-dopant species, said N-dopant species essentially contained within said polysilicon layer;
implanting said polysilicon layer with a nitrogen containing species, said nitrogen containing species essentially contained within said polysilicon layer.
2. The method of claim 1 , wherein a peak concentration of said N-dopant species is about equal to a peak concentration of said nitrogen containing species at about a same distance from a top surface of said polysilicon layer.
3. The method of claim 1 , wherein a surface concentration of said N-dopant species is about equal to a surface concentration of said nitrogen containing species at about a same distance from a top surface of said polysilicon layer.
4. The method of claim 1 , wherein said N-dopant species and said nitrogen containing species have about a same ion implantation concentration profile.
5. The method of claim 1 , wherein a surface concentration of said N-dopant species is between about 1E18 atm/cm3 to about 1E22 atm/cm3 and a surface concentration of said nitrogen containing species is between about abut 1E18 atm/cm3 to about 1E21 atm/cm3.
6. The method of claim 1 , wherein:
wherein a peak concentration of said N-dopant species is between about 1E18 atm/cm3 to about 1E22 atm/cm3 and a peak concentration of said nitrogen containing species is between about 1E18 atm/cm3 to about 1E21 atm/cm3; and
said peak concentration of said N-dopant species occurring between a distance of about 0 nm and about ⅓ of a thickness of said polysilicon layer from a top surface of said polysilicon layer and said peak concentration of said nitrogen containing species occurring between about 0 nm to about ⅔ of said thickness of said polysilicon layer from said top surface of said polysilicon layer.
7. The method of claim 1 , wherein:
said N-dopant species is selected from the group consisting of phosphorus and arsenic; and
said nitrogen containing species is selected from the group consisting of N, N2, NO, NF3, N2O and NH3.
8. The method of claim 1 , further including:
patterning said polysilicon layer into one or more polysilicon lines;
performing a thermal oxidation of sidewalls and top surfaces of said one or more polysilicon lines to form a thermal oxide layer, said thermal oxide layer of about uniform thickness.
9. The method of claim 8 , wherein said nitrogen containing species retards oxidation of said one or more polysilicon lines.
10. The method of claim 1 , wherein said implanting said polysilicon layer with N-dopant species is performed before said implanting said polysilicon layer with said nitrogen containing species.
11. The method of claim 1 , wherein said implanting said polysilicon layer with N-dopant species is performed after said implanting said polysilicon layer with said nitrogen containing species.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/835,745 US20070287275A1 (en) | 2004-10-04 | 2007-08-08 | Method for fabricating doped polysilicon lines |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/711,771 US7303952B2 (en) | 2004-10-04 | 2004-10-04 | Method for fabricating doped polysilicon lines |
US11/835,745 US20070287275A1 (en) | 2004-10-04 | 2007-08-08 | Method for fabricating doped polysilicon lines |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/711,771 Division US7303952B2 (en) | 2004-10-04 | 2004-10-04 | Method for fabricating doped polysilicon lines |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070287275A1 true US20070287275A1 (en) | 2007-12-13 |
Family
ID=36126116
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/711,771 Expired - Fee Related US7303952B2 (en) | 2004-10-04 | 2004-10-04 | Method for fabricating doped polysilicon lines |
US11/835,745 Abandoned US20070287275A1 (en) | 2004-10-04 | 2007-08-08 | Method for fabricating doped polysilicon lines |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/711,771 Expired - Fee Related US7303952B2 (en) | 2004-10-04 | 2004-10-04 | Method for fabricating doped polysilicon lines |
Country Status (1)
Country | Link |
---|---|
US (2) | US7303952B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090085074A1 (en) * | 2007-10-02 | 2009-04-02 | Shih Tzung Su | Trench mosfet and method of manufacture utilizing four masks |
US7799642B2 (en) | 2007-10-02 | 2010-09-21 | Inpower Semiconductor Co., Ltd. | Trench MOSFET and method of manufacture utilizing two masks |
US20130109162A1 (en) * | 2011-09-20 | 2013-05-02 | Applied Materials, Inc. | Surface stabilization process to reduce dopant diffusion |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008021563B4 (en) * | 2008-04-30 | 2012-05-31 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A method of reducing defects of gate structures of CMOS devices during the cleaning processes by modifying a parasitic PN junction |
JP4929306B2 (en) * | 2009-03-17 | 2012-05-09 | 株式会社東芝 | Bias generation circuit and voltage controlled oscillator |
US8334195B2 (en) | 2009-09-09 | 2012-12-18 | International Business Machines Corporation | Pixel sensors of multiple pixel size and methods of implant dose control |
CN114496758B (en) * | 2022-01-11 | 2022-10-11 | 厦门中能微电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) process adopting polysilicon gate low-temperature oxidation |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780330A (en) * | 1996-06-28 | 1998-07-14 | Integrated Device Technology, Inc. | Selective diffusion process for forming both n-type and p-type gates with a single masking step |
US5872049A (en) * | 1996-06-19 | 1999-02-16 | Advanced Micro Devices, Inc. | Nitrogenated gate structure for improved transistor performance and method for making same |
US5885877A (en) * | 1997-04-21 | 1999-03-23 | Advanced Micro Devices, Inc. | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric |
US5930617A (en) * | 1998-03-25 | 1999-07-27 | Texas Instruments-Acer Incorporated | Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction |
US6051459A (en) * | 1997-02-21 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate |
US6121124A (en) * | 1998-06-18 | 2000-09-19 | Lucent Technologies Inc. | Process for fabricating integrated circuits with dual gate devices therein |
US6174807B1 (en) * | 1999-03-02 | 2001-01-16 | Lucent Technologies, Inc. | Method of controlling gate dopant penetration and diffusion in a semiconductor device |
US6352900B1 (en) * | 1999-08-13 | 2002-03-05 | Texas Instruments Incorporated | Controlled oxide growth over polysilicon gates for improved transistor characteristics |
US6373113B1 (en) * | 1996-12-10 | 2002-04-16 | Advanced Micro Devices, Inc. | Nitrogenated gate structure for improved transistor performance and method for making same |
US6399456B2 (en) * | 1998-07-29 | 2002-06-04 | United Microelectronics Corp. | Method of fabricating a resistor and a capacitor electrode in an integrated circuit |
US6436771B1 (en) * | 2001-07-12 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming a semiconductor device with multiple thickness gate dielectric layers |
-
2004
- 2004-10-04 US US10/711,771 patent/US7303952B2/en not_active Expired - Fee Related
-
2007
- 2007-08-08 US US11/835,745 patent/US20070287275A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872049A (en) * | 1996-06-19 | 1999-02-16 | Advanced Micro Devices, Inc. | Nitrogenated gate structure for improved transistor performance and method for making same |
US5936287A (en) * | 1996-06-19 | 1999-08-10 | Advanced Micro Devices, Inc. | Nitrogenated gate structure for improved transistor performance and method for making same |
US5780330A (en) * | 1996-06-28 | 1998-07-14 | Integrated Device Technology, Inc. | Selective diffusion process for forming both n-type and p-type gates with a single masking step |
US6373113B1 (en) * | 1996-12-10 | 2002-04-16 | Advanced Micro Devices, Inc. | Nitrogenated gate structure for improved transistor performance and method for making same |
US6051459A (en) * | 1997-02-21 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate |
US5885877A (en) * | 1997-04-21 | 1999-03-23 | Advanced Micro Devices, Inc. | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric |
US5930617A (en) * | 1998-03-25 | 1999-07-27 | Texas Instruments-Acer Incorporated | Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction |
US6121124A (en) * | 1998-06-18 | 2000-09-19 | Lucent Technologies Inc. | Process for fabricating integrated circuits with dual gate devices therein |
US6399456B2 (en) * | 1998-07-29 | 2002-06-04 | United Microelectronics Corp. | Method of fabricating a resistor and a capacitor electrode in an integrated circuit |
US6174807B1 (en) * | 1999-03-02 | 2001-01-16 | Lucent Technologies, Inc. | Method of controlling gate dopant penetration and diffusion in a semiconductor device |
US6352900B1 (en) * | 1999-08-13 | 2002-03-05 | Texas Instruments Incorporated | Controlled oxide growth over polysilicon gates for improved transistor characteristics |
US6436771B1 (en) * | 2001-07-12 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming a semiconductor device with multiple thickness gate dielectric layers |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090085074A1 (en) * | 2007-10-02 | 2009-04-02 | Shih Tzung Su | Trench mosfet and method of manufacture utilizing four masks |
US7687352B2 (en) * | 2007-10-02 | 2010-03-30 | Inpower Semiconductor Co., Ltd. | Trench MOSFET and method of manufacture utilizing four masks |
US7799642B2 (en) | 2007-10-02 | 2010-09-21 | Inpower Semiconductor Co., Ltd. | Trench MOSFET and method of manufacture utilizing two masks |
US20130109162A1 (en) * | 2011-09-20 | 2013-05-02 | Applied Materials, Inc. | Surface stabilization process to reduce dopant diffusion |
US9390930B2 (en) * | 2011-09-20 | 2016-07-12 | Applied Materials, Inc. | Surface stabilization process to reduce dopant diffusion |
Also Published As
Publication number | Publication date |
---|---|
US20060073689A1 (en) | 2006-04-06 |
US7303952B2 (en) | 2007-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100352715B1 (en) | Submicron metal gate MOS transistor and method of formation thereof | |
KR101618465B1 (en) | Embedded transistor | |
US7585735B2 (en) | Asymmetric spacers and asymmetric source/drain extension layers | |
US6184097B1 (en) | Process for forming ultra-shallow source/drain extensions | |
US6344396B1 (en) | Removable spacer technology using ion implantation for forming asymmetric MOS transistors | |
US20070196988A1 (en) | Poly pre-doping anneals for improved gate profiles | |
EP1776719A2 (en) | Integrated circuit with multiple spacer insulating region widths | |
US20070287275A1 (en) | Method for fabricating doped polysilicon lines | |
KR100843879B1 (en) | Semiconductor device and method for fabricating the same | |
KR100591344B1 (en) | Manufacturing method of semiconductor device | |
US6936520B2 (en) | Method for fabricating semiconductor device having gate electrode together with resistance element | |
KR20030043939A (en) | Method and device to reduce gate-induced drain leakage(GIDL) current in thin gate oxide MOSFETS | |
KR100391891B1 (en) | Manufacturing Method of Semiconductor Device | |
US20070224808A1 (en) | Silicided gates for CMOS devices | |
JP2006100599A (en) | Semiconductor device and manufacturing method thereof | |
US6051460A (en) | Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon | |
US20090186457A1 (en) | Anneal sequence integration for cmos devices | |
US5882962A (en) | Method of fabricating MOS transistor having a P+ -polysilicon gate | |
WO2004114413A1 (en) | Semiconductor device and its manufacturing method | |
US20040180483A1 (en) | Method of manufacturing CMOS transistor with LDD structure | |
US6586289B1 (en) | Anti-spacer structure for improved gate activation | |
US6312999B1 (en) | Method for forming PLDD structure with minimized lateral dopant diffusion | |
US7439123B2 (en) | Low resistance contact semiconductor device structure | |
JPS62242367A (en) | Formation of side surface mask layer of gate electrode of mos transistor | |
US8178932B2 (en) | Semiconductor device having transistors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |