JP2007235034A - 電子基板、半導体装置および電子機器 - Google Patents
電子基板、半導体装置および電子機器 Download PDFInfo
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- JP2007235034A JP2007235034A JP2006057672A JP2006057672A JP2007235034A JP 2007235034 A JP2007235034 A JP 2007235034A JP 2006057672 A JP2006057672 A JP 2006057672A JP 2006057672 A JP2006057672 A JP 2006057672A JP 2007235034 A JP2007235034 A JP 2007235034A
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Abstract
【解決手段】基体10の能動面側に、相互にインダクタンス値または適用可能周波数の異なる第1インダクタ素子80および第2インダクタ素子40が形成されている。第1インダクタ素子80は外部との電力伝送に使用され、第2インダクタ素子40は外部との通信に使用される。これにより、電子基板1の接続端子を削減することが可能になり、構造を簡素化することができる。これに伴って、母基板に対する電子基板1の実装作業を簡略化することができる。
【選択図】図1
Description
本発明は、上記問題点を解決するためになされたものであって、構造が簡単であり、また実装作業を簡略化することが可能な、電子基板および半導体装置の提供を目的とする。また、低コストの電子機器の提供を目的とする。
この構成によれば、電子基板に形成された複数のインダクタ素子を用いて信号授受を行うことができるので、電子基板の接続端子を削減することが可能になり、電子基板の構造を簡素化することができる。これに伴って、電子基板の実装作業を簡略化することが可能になり、さらには実装に伴う信頼性の低下を防止することができる。
ここで「適用可能周波数」とは、当該インダクタをアンテナとして機能させる場合に当該インダクタがアンテナとしての特性を示し、アンテナとして適用することが可能な周波数をいう。
この構成によれば、各インダクタ素子に機能を分担させることができるので、各インダクタ素子を最適設計することが可能になる。これにより、各インダクタ素子の寸法効率や伝送効率を向上させることができる。
この構成によれば、外部とのすべての信号授受をインダクタ素子によって行うことが可能になり、電子基板の接続端子を廃止することができる。
この構成によれば、電力伝送のみを接続端子によって確実に行うことができる。また、外部との通信を複数のインダクタ素子によって行うことにより、通信速度を向上させることができる。
この構成によれば、インダクタ素子から出力された電磁波が、基体において渦電流発生損として吸収されるのを抑制することが可能になり、アンテナとしての性能を向上させることができる。
上述した電子基板は、接続端子を削減することが可能である。したがって、電子基板の実装作業を簡略化することが可能になり、製造コストを低減することができる。また、実装に伴う信頼性の低下を防止することができる。
この構成によれば、伝送効率をさらに向上させることができる。また混信を防止することができる。
この構成によれば、接続端子が削減された電子基板を備えているので、低コストの電子機器を提供することができる。
最初に、第1実施形態に係る電子基板について説明する。
図1は第1実施形態に係る電子基板の平面図である。第1実施形態に係る電子基板1は、基体10の能動面側にインダクタンス値または適用可能周波数の異なる複数のインダクタ素子40,80が形成されたものである。そのうち、第1インダクタ素子80は通信に使用されるものであり、第2インダクタ素子40は電力伝送に使用されるものである。
その誘電体層31の表面に、インダクタ素子40の巻き線41が形成されている。巻き線41の構成材料は、連結配線12aと同様であるが、巻き線41として必要な抵抗レンジや耐許容電流値等の特性に応じて適宜選択することができる。
なお本明細書中の各実施形態では、巻き線(スパイラル)型インダクタを例にして説明しているが、これに限定されるものではなく、インダクタもしくはアンテナとして機能するものであれば各実施形態に適用することができる。巻き線(スパイラル)型インダクタの他に、ミアンダ型、トロイダル型、パッチ型等が知られており、それらを適用する場合のインダクタンス値の大小はそれぞれのインダクタ、アンテナによる。
図4は、第1実施形態に係る半導体装置の説明図であり、図1のA−A線に相当する部分における断面図である。図4に示すように、第1実施形態に係る半導体装置5は、母基板(マザーボード)100の表面に、第1電子基板200および第2電子基板300が順に実装されたものである。
次に、第2実施形態に係る電子基板について説明する。
図5は第2実施形態に係る電子基板の説明図であり、図5(a)は平面図であり、図5(b)は図5(a)のE−E線における断面図である。図5(a)に示すように、第2実施形態に係る電子基板1は、接続端子63を使用して電力伝送を行う点で、インダクタ素子を使用して電力伝送を行う第1実施形態とは異なっている。また第2実施形態に係る電子基板は、複数のインダクタ素子80,90を使用して通信を行う点で、第1実施形態とは異なっている。なお第1実施形態と同様の構成となる部分については、その詳細な説明を省略する。
図5(a)に示すように、外部から電力供給を受けるため、電子基板1の周縁部に沿って複数の電極62が整列配置されている。近年の電子基板1の小型化により、隣接する電極62間のピッチは非常に狭くなっている。この電子基板1を相手側部材に実装すると、隣接する電極62との間で短絡が発生するおそれがある。そこで電極62間のピッチを広げるため、電極62の再配置配線64が形成されている。
次に、第2実施形態に係る電子基板の製造方法について説明する。
図6および図7は、第2実施形態に係る電子基板の製造方法の工程図であり、図5のF−F線に相当する部分における断面図である。なお電子基板の製造には、W−CSP技術を利用する。すなわち、ウエハに対し一括して以下の各工程を行い、最後に個々の電子基板に分離する。
次に図7(b)に示すように、その開口部の内側における接続端子63の表面に、バンプ78を形成する。
その後、ウエハから個々の基体10を分離する。基体10の分離は、ダイシング等によって行うことができる。以上により、本実施形態に係る電子基板1が完成する。
図8は、第2実施形態に係る半導体装置の説明図であり、図5のF−F線に相当する部分における断面図である。図8に示すように、第2実施形態に係る半導体装置5は、母基板(マザーボード)100の表面に、第1電子基板200が実装されたものである。
母基板(マザーボード)100の表面には、第1電子基板200との接続端子163が形成されている。また母基板100の表面には、第1インダクタ素子(不図示)および第2インダクタ素子190が形成されている。各インダクタ素子は通信に使用されるものであり、適用可能周波数が2〜5GHzに設定されている。
次に、上述した電子基板を備えた電子機器の例について説明する。
図9は、携帯電話の斜視図である。上述した電子基板は、携帯電話1300の筐体内部に配置されている。この構成によれば、構造が簡単で実装作業性に優れた電子基板を備えているので、低コストの携帯電話を提供することができる。
Claims (8)
- 基体の能動面側または前記能動面の裏面側に、複数のインダクタ素子が形成されていることを特徴とする電子基板。
- 前記複数のインダクタ素子は、相互にインダクタンス値または適用可能周波数の異なる第1インダクタ素子および第2インダクタ素子を含んでいることを特徴とする請求項1に記載の電子基板。
- 前記第1インダクタ素子は、外部との電力伝送に使用され、
前記第2インダクタ素子は、外部との通信に使用されることを特徴とする請求項2に記載の電子基板。 - 前記基体には、外部との電力伝送に使用される接続端子が設けられ、
前記第1インダクタ素子および前記第2インダクタ素子は、外部との通信に使用されることを特徴とする請求項2に記載の電子基板。 - 前記複数のインダクタ素子の全部または一部と前記基体との間には、前記基体より誘電正接が小さい材料層が設けられていることを特徴とする請求項1ないし請求項4のいずれか1項に記載の電子基板。
- 請求項1ないし請求項5のいずれか1項に記載の電子基板が積層配置され、前記電子基板に形成された前記インダクタ素子をアンテナとして電磁波を送受信することにより、前記電子基板間における信号授受を可能としたことを特徴とする半導体装置。
- 信号授受を行う一対の前記電子基板に形成された前記インダクタ素子が、相互に対向配置されていることを特徴とする請求項6に記載の半導体装置。
- 請求項1ないし請求項5のいずれか1項に記載の電子基板を備えたことを特徴とする電子機器。
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CNA2007100846918A CN101030576A (zh) | 2006-03-03 | 2007-03-01 | 电子基板、半导体装置及电子机器 |
US12/781,179 US8610578B2 (en) | 2006-03-03 | 2010-05-17 | Electronic substrate, semiconductor device, and electronic device |
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WO2011001992A1 (ja) * | 2009-06-30 | 2011-01-06 | 日本電気株式会社 | 半導体装置、該装置に用いられる実装基板及び該実装基板の製造方法 |
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Also Published As
Publication number | Publication date |
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KR20070090759A (ko) | 2007-09-06 |
US20070205956A1 (en) | 2007-09-06 |
US20140070915A1 (en) | 2014-03-13 |
JP4544181B2 (ja) | 2010-09-15 |
US8610578B2 (en) | 2013-12-17 |
US20100219927A1 (en) | 2010-09-02 |
CN101030576A (zh) | 2007-09-05 |
TW200802797A (en) | 2008-01-01 |
TWI341021B (en) | 2011-04-21 |
KR100971161B1 (ko) | 2010-07-20 |
US7746232B2 (en) | 2010-06-29 |
US9251942B2 (en) | 2016-02-02 |
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