JP7001096B2 - 電子部品モジュール及び電子部品モジュールの製造方法 - Google Patents
電子部品モジュール及び電子部品モジュールの製造方法 Download PDFInfo
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- JP7001096B2 JP7001096B2 JP2019537565A JP2019537565A JP7001096B2 JP 7001096 B2 JP7001096 B2 JP 7001096B2 JP 2019537565 A JP2019537565 A JP 2019537565A JP 2019537565 A JP2019537565 A JP 2019537565A JP 7001096 B2 JP7001096 B2 JP 7001096B2
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02992—Details of bus bars, contact pads or other electrical connections for finger electrodes
Description
(1)電子部品モジュールの全体構成
以下、実施形態1に係る電子部品モジュール1について、図面を参照して説明する。
次に、電子部品モジュール1の各構成要素について、図面を参照して説明する。
電子部品2は、図1Aに示すように、電子部品モジュール1の第1方向D1において互いに反対側にある表面(第1主面)21及び裏面(第2主面)22を有する。より詳細には、電子部品2は、チップ状電子部品であり、板状に形成されており、その厚さ方向において互いに反対側にある表面21及び裏面22を有する。表面21及び裏面22は、互いに背向する。また、電子部品2は、側面23を有する。側面23は、表面21と裏面22とを結ぶ。電子部品2の平面視形状(電子部品2をその厚さ方向から見たときの外周形状)は、長方形状であるが、長方形状に限らず、例えば正方形状であってもよい。
樹脂構造体3は、図1Aに示すように、電子部品2を保持するように構成されている。樹脂構造体3は、電子部品モジュール1の第1方向D1において互いに反対側にある第1面31及び第2面32を有する。より詳細には、樹脂構造体3は、板状に形成されており、その厚さ方向において互いに反対側にある第1面31及び第2面32を有する。樹脂構造体3の平面視形状(樹脂構造体3をその厚さ方向すなわち第1方向D1から見たときの外周形状)は、長方形状である。ただし、樹脂構造体3の平面視形状は、長方形状に限らず、例えば正方形状であってもよい。樹脂構造体3の平面サイズは、電子部品2の平面サイズよりも大きい。
電子部品モジュール1では、図1Aに示すように、電子部品2の側方に、複数(図示例では2つ)の貫通配線4が配置されている。第1方向D1と直交する第2方向D2において、複数の貫通配線4は、電子部品2から離れて位置している。複数の貫通配線4は、樹脂構造体3に保持されている。
配線層5は、樹脂構造体3の第1面31側及び電子部品2の表面21側において、電子部品2と貫通配線4とを電気的に接続している。配線層5は、電子部品2の表面21(のうち端子電極の表面)に接続されている第1端51と、貫通配線4に接続されている第2端52とを有する。配線層5は、電子部品2の表面21と貫通配線4の第1端面41と後述の絶縁部7の第2中間層72とに跨って配置されている。
電極8は、樹脂構造体3の第2面32側において、貫通配線4の第2端面42と第2レジスト層10とに跨って形成されている。
第1レジスト層9は、樹脂構造体3の第1面31側において、配線層5の一部を除いて配線層5を覆うように形成されている。第1レジスト層9には、配線層5の一部を露出させる孔91が形成されている。第1レジスト層9は、樹脂構造体3の第1面31側において、配線層5と絶縁部7とに跨って形成されている。第1レジスト層9は、電気絶縁性を有する。第1レジスト層9は、配線層5よりもはんだ濡れ性が低い材料により形成されている。第1レジスト層9は、例えばポリイミド層である。
絶縁部7は、電気絶縁性を有する。絶縁部7は、第1中間層(第1絶縁部)71と、第2中間層(第2絶縁部)72と、複数(図示例では2つ)の第3中間層(第3絶縁部)73と、を備える。
シールド部6は、電磁シールドのためのシールド層として設けられている。シールド部6は、第1導体層61と、第2導体層62と、複数(図示例では2つ)の第3導体層63と、を備える。
電子部品モジュール1では、第3導体層63は、貫通配線4の側面を囲むように貫通配線4と同軸的に配置されている。つまり、電子部品モジュール1は、貫通配線4と第3導体層63とを含む同軸構造14を有する。電子部品モジュール1では、同軸構造14が、貫通配線4と第3導体層63との間に介在する第3中間層73を更に備える。電子部品モジュール1では、樹脂構造体3が、第3導体層63の側面を覆っている。
第1グラウンド用配線層12は、シールド部6と電気的に接続されている。より詳細には、第1グラウンド用配線層12は、樹脂構造体3の第1面31側において、シールド部6と接しており、第3導体層63と電気的に接続されている。第1グラウンド用配線層12は、シールド部6のうち第3導体層63から見て第2導体層62とは反対側にあるグラウンド用導体層65と第1レジスト層9とに跨って形成されている。第1グラウンド用配線層12の材料は、例えば、Cuである。
次に、実施形態1に係る電子部品モジュール1の製造方法について、図3A~3F、4A~4F及び5A~5Dを参照して説明する。
以上説明した実施形態1に係る電子部品モジュール1では、シールド部6において、電子部品2と樹脂構造体3との間に設けられている第1導体層61と、配線層5と樹脂構造体3との間に設けられている第2導体層62とが、一体となっている。これにより、シールド部6において第1導体層61と第2導体層62との間で界面が発生しないので、シールド部6が劣化しにくくなり、外部からの電磁波を遮断する電磁シールド性能の劣化を抑制することができる。つまり、外部からの電磁波を遮断する電磁シールド性の長期的な信頼性を高めることができる。ここで、「第1導体層61と第2導体層62とが一体形成されている」とは、第1導体層61と第2導体層62とが同一の材料を用いて連続している状態で形成されていることをいう。「第1導体層61と第2導体層62とが一体となっている」とは、第1導体層61と第2導体層62とが同一の材料であって連続している状態をいう。
(5.1)変形例1
実施形態1の変形例1に係る電子部品モジュール1aは、図6に示すように、実施形態1に係る電子部品モジュール1(図1A参照)における第1グラウンド用配線層12及び第3レジスト層11を備えていない点で、実施形態1に係る電子部品モジュール1と相違する。変形例1に係る電子部品モジュール1aに関し、実施形態1に係る電子部品モジュール1と同様の構成要素については、同一の符号を付して説明を省略する。
実施形態1の変形例2に係る電子部品モジュール1bは、図7に示すように、第1レジスト層9が配線層5全体を覆っている点、及び第1グラウンド用配線層12が第1レジスト層9全体を覆っている点で、実施形態1に係る電子部品モジュール1と相違する。変形例2に係る電子部品モジュール1bに関し、実施形態1に係る電子部品モジュール1と同様の構成要素については、同一の符号を付して説明を省略する。
実施形態1の変形例3に係る電子部品モジュール1cは、図8に示すように、第2方向D2において並ぶ2つの電子部品20cを実装できるように第2方向D2における第2グラウンド用配線層13の全長(配線長)を長くしてある点で、実施形態1に係る電子部品モジュール1と相違する。また、変形例3に係る電子部品モジュール1cは、第2グラウンド用配線層13において第2レジスト層10により覆われていない領域上に電極16を形成してある点で、実施形態1に係る電子部品モジュール1と相違する。変形例3に係る電子部品モジュール1cに関し、実施形態1に係る電子部品モジュール1と同様の構成要素については、同一の符号を付して説明を省略する。
実施形態1に係る電子部品モジュール1では、樹脂構造体3の第2面32が平面状であり、樹脂構造体3の第2面32から電子部品2の表面21までの最短距離が、第2面32から第1面31までの最短距離よりも長い。これにより、実施形態1に係る電子部品モジュール1では、低背化を図ることができる。
実施形態2に係る電子部品モジュール1dは、図9に示すように、複数(図示例では2つ)の電子部品2が設けられている点で、実施形態1に係る電子部品モジュール1(図1A参照)と相違する。実施形態2に係る電子部品モジュール1dに関し、実施形態1に係る電子部品モジュール1と同様の構成要素については、同一の符号を付して説明を省略する。
実施形態3に係る電子部品モジュール1eは、図10に示すように、実施形態1に係る電子部品モジュール1(図1A参照)における貫通配線4が設けられていない点で、実施形態1に係る電子部品モジュール1と相違する。実施形態3に係る電子部品モジュール1eに関し、実施形態1に係る電子部品モジュール1と同様の構成要素については、同一の符号を付して説明を省略する。
以上説明した実施形態等から以下の態様が開示されていることは明らかである。
2 電子部品
21 表面(第1主面)
22 裏面(第2主面)
23 側面
3 樹脂構造体
31 第1面
32 第2面
4 貫通配線
41 第1端面
42 第2端面
43,43G,43S 導電性バンプ
44,44G,44S 導電性バンプ
46,46G,46S 接合部
5 配線層(配線部)
51 第1端
52 第2端
53 電極
6 シールド部
61 第1導体層
62 第2導体層
63 第3導体層
64 第4導体層
7 絶縁部(中間部)
71 第1中間層
72 第2中間層
73 第3中間層
74 第4中間層
8 電極
9 第1レジスト層
10 第2レジスト層
11 第3レジスト層
12 第1グラウンド用配線層
13 第2グラウンド用配線層
14 同軸構造
15 回路基板
16 電極
20,20c 電子部品
91 孔
101 孔
111 孔
120 支持体
121 表面
123 ベース
124 接着層
125 導電層
200 通信モジュール
201 カバー層
202 間隙
203 間隙
210 通信モジュール
220 通信モジュール
30 樹脂構造層
301 第1面
302 第2面
400 ピラー
600 金属層
700 絶縁層
D1 第1方向
D2 第2方向
Claims (9)
- 互いに背向する第1主面及び第2主面、並びに、前記第1主面と前記第2主面とを結ぶ側面を有する電子部品と、
前記電子部品の前記側面の少なくとも一部及び前記第2主面を覆っている樹脂構造体と、
前記電子部品に電気的に接続されている配線部と、
前記電子部品と前記樹脂構造体との間に前記電子部品から離れて設けられており導電性を有する第1導体層、及び、前記配線部と前記樹脂構造体との間に前記配線部から離れて設けられており導電性を有する第2導体層を含むシールド部と、
前記樹脂構造体を貫通している貫通配線と、を備え、
前記シールド部では、前記第1導体層と前記第2導体層とが一体となっており、
前記シールド部は、前記貫通配線と前記樹脂構造体との間に前記貫通配線から離れて設けられている第3導体層を更に含む
ことを特徴とする電子部品モジュール。 - 前記シールド部では、前記第1導体層と前記第2導体層とが同一の材料であって連続している
ことを特徴とする請求項1に記載の電子部品モジュール。 - 前記シールド部では、前記第1導体層と前記第2導体層と前記第3導体層とが一体となっている
ことを特徴とする請求項1又は2に記載の電子部品モジュール。 - 前記シールド部の前記第3導体層は、前記貫通配線と前記樹脂構造体との間において、前記貫通配線の側面を囲むように配置され、前記貫通配線の前記側面から離れている
ことを特徴とする請求項1~3のいずれか1項に記載の電子部品モジュール。 - 前記貫通配線と前記第3導体層とにより同軸構造を有する
ことを特徴とする請求項1~4のいずれか1項に記載の電子部品モジュール。 - 前記電子部品及び前記配線部の少なくとも一方と前記シールド部との間に介在し電気絶縁性を有する中間部を更に備える
ことを特徴とする請求項1~5のいずれか1項に記載の電子部品モジュール。 - 前記中間部の誘電率は、前記樹脂構造体の誘電率よりも低い
ことを特徴とする請求項6に記載の電子部品モジュール。 - 前記電子部品は、周波数帯5GHz以上の高周波デバイスである
ことを特徴とする請求項1~7のいずれか1項に記載の電子部品モジュール。 - 互いに背向する第1主面及び第2主面、並びに、前記第1主面と前記第2主面とを結ぶ側面を有する電子部品の前記第1主面を支持体の表面に対向させて前記電子部品を前記支持体の前記表面上に配置する部品配置工程と、
前記支持体の前記表面のうち露出している領域及び前記電子部品の前記側面のうち露出している領域及び前記第2主面の両方を覆う中間部を形成する中間部形成工程と、
前記中間部を覆うシールド部を形成するシールド部形成工程と、
前記シールド部を覆う樹脂構造体を成形する樹脂成形工程と、
前記中間部を形成する前に、前記支持体の前記表面上に導電性を有するピラーを形成するピラー形成工程と、を有し、
前記中間部形成工程では、前記ピラーの露出している領域、前記支持体の前記表面のうち露出している領域、及び、前記電子部品の前記側面のうち露出している領域を覆う前記中間部を形成する
ことを特徴とする電子部品モジュールの製造方法。
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JP2013187434A (ja) | 2012-03-09 | 2013-09-19 | Fujitsu Ltd | 半導体装置、半導体装置の製造方法、電子装置及び基板 |
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