JP2006512774A5 - - Google Patents

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JP2006512774A5
JP2006512774A5 JP2004565751A JP2004565751A JP2006512774A5 JP 2006512774 A5 JP2006512774 A5 JP 2006512774A5 JP 2004565751 A JP2004565751 A JP 2004565751A JP 2004565751 A JP2004565751 A JP 2004565751A JP 2006512774 A5 JP2006512774 A5 JP 2006512774A5
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region
well region
semiconductor device
well
conductive
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JP2004565751A
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JP4688501B2 (ja
JP2006512774A (ja
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Priority claimed from US10/334,272 external-priority patent/US6936898B2/en
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JP2004565751A 2002-12-31 2003-12-29 半導体デバイスのウェル領域 Expired - Fee Related JP4688501B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/334,272 US6936898B2 (en) 2002-12-31 2002-12-31 Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US10/334,272 2002-12-31
PCT/US2003/041402 WO2004061967A2 (en) 2002-12-31 2003-12-29 Well regions of semiconductor devices

Publications (3)

Publication Number Publication Date
JP2006512774A JP2006512774A (ja) 2006-04-13
JP2006512774A5 true JP2006512774A5 (enExample) 2007-02-15
JP4688501B2 JP4688501B2 (ja) 2011-05-25

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JP2004565751A Expired - Fee Related JP4688501B2 (ja) 2002-12-31 2003-12-29 半導体デバイスのウェル領域

Country Status (5)

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US (9) US6936898B2 (enExample)
JP (1) JP4688501B2 (enExample)
CN (2) CN101604663B (enExample)
AU (1) AU2003300399A1 (enExample)
WO (1) WO2004061967A2 (enExample)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7180322B1 (en) 2002-04-16 2007-02-20 Transmeta Corporation Closed loop feedback control of integrated circuits
US7941675B2 (en) 2002-12-31 2011-05-10 Burr James B Adaptive power control
US7949864B1 (en) * 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
US7228242B2 (en) 2002-12-31 2007-06-05 Transmeta Corporation Adaptive power control based on pre package characterization of integrated circuits
US7953990B2 (en) 2002-12-31 2011-05-31 Stewart Thomas E Adaptive power control based on post package characterization of integrated circuits
US7205758B1 (en) 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
US7323367B1 (en) 2002-12-31 2008-01-29 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US6936898B2 (en) * 2002-12-31 2005-08-30 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
WO2004070832A1 (ja) * 2003-02-04 2004-08-19 Matsushita Electric Industrial Co., Ltd. 半導体集積回路装置
KR100536612B1 (ko) * 2003-10-09 2005-12-14 삼성전자주식회사 소프트 에러율 내성 및 래치업 내성을 증진시키기 위한 웰구조를 갖는 반도체 장치 및 그 제조 방법
US7174528B1 (en) 2003-10-10 2007-02-06 Transmeta Corporation Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure
US7049699B1 (en) * 2003-11-12 2006-05-23 Transmeta Corporation Low RC structures for routing body-bias voltage
US7012461B1 (en) 2003-12-23 2006-03-14 Transmeta Corporation Stabilization component for a substrate potential regulation circuit
US7129771B1 (en) 2003-12-23 2006-10-31 Transmeta Corporation Servo loop for well bias voltage source
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7692477B1 (en) 2003-12-23 2010-04-06 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7645673B1 (en) 2004-02-03 2010-01-12 Michael Pelham Method for generating a deep N-well pattern for an integrated circuit design
US7759740B1 (en) * 2004-03-23 2010-07-20 Masleid Robert P Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells
US7388260B1 (en) 2004-03-31 2008-06-17 Transmeta Corporation Structure for spanning gap in body-bias voltage routing structure
US7313779B1 (en) 2004-10-12 2007-12-25 Transmeta Corporation Method and system for tiling a bias design to facilitate efficient design rule checking
US7211870B2 (en) * 2004-10-14 2007-05-01 Nec Electronics Corporation Semiconductor device
JP2006140448A (ja) * 2004-10-14 2006-06-01 Nec Electronics Corp 半導体装置
JP2006120852A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7598573B2 (en) * 2004-11-16 2009-10-06 Robert Paul Masleid Systems and methods for voltage distribution via multiple epitaxial layers
US7667288B2 (en) * 2004-11-16 2010-02-23 Masleid Robert P Systems and methods for voltage distribution via epitaxial layers
JP2007005763A (ja) * 2005-05-26 2007-01-11 Fujitsu Ltd 半導体装置及びその製造方法及びに半導体装置の設計方法
US7217962B1 (en) * 2005-06-30 2007-05-15 Transmeta Corporation Wire mesh patterns for semiconductor devices
US7661086B1 (en) 2005-06-30 2010-02-09 Scott Pitkethly Enhanced clock signal flexible distribution system and method
US7730440B2 (en) * 2005-06-30 2010-06-01 Scott Pitkethly Clock signal distribution system and method
US7305647B1 (en) 2005-07-28 2007-12-04 Transmeta Corporation Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
US7462903B1 (en) * 2005-09-14 2008-12-09 Spansion Llc Methods for fabricating semiconductor devices and contacts to semiconductor devices
US7265041B2 (en) * 2005-12-19 2007-09-04 Micrel, Inc. Gate layouts for transistors
JP4777082B2 (ja) * 2006-02-13 2011-09-21 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2007214490A (ja) * 2006-02-13 2007-08-23 Fujitsu Ltd 半導体装置及びその製造方法
JP4819548B2 (ja) 2006-03-30 2011-11-24 富士通セミコンダクター株式会社 半導体装置
US8451951B2 (en) * 2008-08-15 2013-05-28 Ntt Docomo, Inc. Channel classification and rate adaptation for SU-MIMO systems
US8735797B2 (en) * 2009-12-08 2014-05-27 Zena Technologies, Inc. Nanowire photo-detector grown on a back-side illuminated image sensor
US8742831B2 (en) * 2009-02-23 2014-06-03 Honeywell International Inc. Method for digital programmable optimization of mixed-signal circuits
EP2246885A1 (fr) * 2009-04-27 2010-11-03 STmicroelectronics SA Structure de protection d'un circuit intégré contre des décharges électrostatiques
KR101699033B1 (ko) * 2009-11-30 2017-01-24 에스케이하이닉스 주식회사 출력 드라이버
KR102052307B1 (ko) * 2011-11-09 2019-12-04 스카이워크스 솔루션즈, 인코포레이티드 전계 효과 트랜지스터 구조 및 관련된 무선-주파수 스위치
JP5875355B2 (ja) * 2011-12-12 2016-03-02 ルネサスエレクトロニクス株式会社 回路シミュレーション方法
WO2017111869A1 (en) 2015-12-24 2017-06-29 Intel Corporation Transition metal dichalcogenides (tmdcs) over iii-nitride heteroepitaxial layers
KR20240053079A (ko) 2021-05-25 2024-04-23 이노사이언스 (쑤저우) 테크놀로지 컴퍼니 리미티드 질화물-기반 반도체 양방향 스위칭 디바이스 및 그 제조방법
US12046603B2 (en) * 2021-11-23 2024-07-23 Globalfoundries U.S. Inc. Semiconductor structure including sectioned well region
US11929399B2 (en) 2022-03-07 2024-03-12 Globalfoundries U.S. Inc. Deep nwell contact structures

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4150366A (en) * 1976-09-01 1979-04-17 Motorola, Inc. Trim network for monolithic circuits and use in trimming a d/a converter
US4605980A (en) * 1984-03-02 1986-08-12 Zilog, Inc. Integrated circuit high voltage protection
JPS6410656A (en) 1987-07-03 1989-01-13 Hitachi Ltd Complementary type semiconductor device
US5160816A (en) 1990-10-17 1992-11-03 Systems Development Group Two dimensional sound diffusor
US5081371A (en) * 1990-11-07 1992-01-14 U.S. Philips Corp. Integrated charge pump circuit with back bias voltage reduction
US5648288A (en) 1992-03-20 1997-07-15 Siliconix Incorporated Threshold adjustment in field effect semiconductor devices
US5397934A (en) * 1993-04-05 1995-03-14 National Semiconductor Corporation Apparatus and method for adjusting the threshold voltage of MOS transistors
US5412239A (en) 1993-05-14 1995-05-02 Siliconix Incorporated Contact geometry for improved lateral MOSFET
JP3110262B2 (ja) * 1993-11-15 2000-11-20 松下電器産業株式会社 半導体装置及び半導体装置のオペレーティング方法
US5355008A (en) * 1993-11-19 1994-10-11 Micrel, Inc. Diamond shaped gate mesh for cellular MOS transistor array
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
JP2822881B2 (ja) * 1994-03-30 1998-11-11 日本電気株式会社 半導体集積回路装置
US5636129A (en) 1994-04-20 1997-06-03 Her; One-Hsiow A. Electrical routing through fixed sized module and variable sized channel grids
US5447786A (en) * 1994-05-25 1995-09-05 Auburn University Selective infrared line emitters
US5552333A (en) 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5689144A (en) * 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
US5781034A (en) * 1996-07-11 1998-07-14 Cypress Semiconductor Corporation Reduced output swing with p-channel pullup diode connected
US5939934A (en) * 1996-12-03 1999-08-17 Stmicroelectronics, Inc. Integrated circuit passively biasing transistor effective threshold voltage and related methods
JPH10199993A (ja) 1997-01-07 1998-07-31 Mitsubishi Electric Corp 半導体回路装置及びその製造方法、半導体回路装置製造用マスク装置
US5913122A (en) 1997-01-27 1999-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regions
KR100240872B1 (ko) * 1997-02-17 2000-01-15 윤종용 정전기 방전 보호 회로 및 그것을 구비하는 집적 회로
JP3886590B2 (ja) * 1997-03-12 2007-02-28 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6218895B1 (en) * 1997-06-20 2001-04-17 Intel Corporation Multiple well transistor circuits having forward body bias
US6593799B2 (en) * 1997-06-20 2003-07-15 Intel Corporation Circuit including forward body bias from supply voltage and ground nodes
EP0887932A1 (en) * 1997-06-24 1998-12-30 STMicroelectronics S.r.l. Control of the body voltage of a high voltage LDMOS
JP4128251B2 (ja) 1997-10-23 2008-07-30 富士通株式会社 配線密度予測方法およびセル配置装置
JP3269475B2 (ja) * 1998-02-16 2002-03-25 日本電気株式会社 半導体装置
US6091283A (en) 1998-02-24 2000-07-18 Sun Microsystems, Inc. Sub-threshold leakage tuning circuit
US6218708B1 (en) 1998-02-25 2001-04-17 Sun Microsystems, Inc. Back-biased MOS device and method
US6180998B1 (en) 1998-03-30 2001-01-30 Lsi Logic Corporation DRAM with built-in noise protection
JP3461443B2 (ja) 1998-04-07 2003-10-27 松下電器産業株式会社 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
US6048746A (en) 1998-06-08 2000-04-11 Sun Microsystems, Inc. Method for making die-compensated threshold tuning circuit
US6087892A (en) 1998-06-08 2000-07-11 Sun Microsystems, Inc. Target Ion/Ioff threshold tuning circuit and method
US6412102B1 (en) 1998-07-22 2002-06-25 Lsi Logic Corporation Wire routing optimization
US6169310B1 (en) * 1998-12-03 2001-01-02 National Semiconductor Corporation Electrostatic discharge protection device
JP2000216347A (ja) * 1999-01-20 2000-08-04 Toshiba Corp Cmos半導体装置
US6498592B1 (en) 1999-02-16 2002-12-24 Sarnoff Corp. Display tile structure using organic light emitting materials
US6507944B1 (en) 1999-07-30 2003-01-14 Fujitsu Limited Data processing method and apparatus, reticle mask, exposing method and apparatus, and recording medium
US6249454B1 (en) 1999-09-15 2001-06-19 Taiwan Semiconductor Manufacturing Company Split-gate flash cell for virtual ground architecture
US6405358B1 (en) 1999-10-08 2002-06-11 Agilent Technologies, Inc. Method for estimating and displaying wiring congestion
JP3822009B2 (ja) 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体
JP4068781B2 (ja) 2000-02-28 2008-03-26 株式会社ルネサステクノロジ 半導体集積回路装置および半導体集積回路装置の製造方法
US6536028B1 (en) 2000-03-14 2003-03-18 Ammocore Technologies, Inc. Standard block architecture for integrated circuit design
JP3636345B2 (ja) * 2000-03-17 2005-04-06 富士電機デバイステクノロジー株式会社 半導体素子および半導体素子の製造方法
KR100363327B1 (ko) * 2000-03-23 2002-11-30 삼성전자 주식회사 퓨즈 회로 및 그것의 프로그램 상태 검출 방법
JP2001274265A (ja) * 2000-03-28 2001-10-05 Mitsubishi Electric Corp 半導体装置
JP2002064150A (ja) * 2000-06-05 2002-02-28 Mitsubishi Electric Corp 半導体装置
US6566720B2 (en) 2000-10-05 2003-05-20 United Memories, Inc. Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits
US6303444B1 (en) 2000-10-19 2001-10-16 Sun Microsystems, Inc. Method for introducing an equivalent RC circuit in a MOS device using resistive wells
JP3950294B2 (ja) * 2000-11-16 2007-07-25 シャープ株式会社 半導体装置
JP2002198439A (ja) * 2000-12-26 2002-07-12 Sharp Corp 半導体装置および携帯電子機器
US6417720B1 (en) * 2000-12-28 2002-07-09 Intel Corporation High voltage sense circuit for programming of programmable devices
US6429726B1 (en) * 2001-03-27 2002-08-06 Intel Corporation Robust forward body bias generation circuit with digital trimming for DC power supply variation
JP2002289698A (ja) * 2001-03-28 2002-10-04 Sharp Corp 半導体装置及びその製造方法と携帯電子機器
US6570810B2 (en) 2001-04-20 2003-05-27 Multi Level Memory Technology Contactless flash memory with buried diffusion bit/virtual ground lines
US6605981B2 (en) * 2001-04-26 2003-08-12 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
US6489224B1 (en) 2001-05-31 2002-12-03 Sun Microsystems, Inc. Method for engineering the threshold voltage of a device using buried wells
US7155698B1 (en) 2001-09-11 2006-12-26 The Regents Of The University Of California Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects
US6621325B2 (en) 2001-09-18 2003-09-16 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US6784744B2 (en) * 2001-09-27 2004-08-31 Powerq Technologies, Inc. Amplifier circuits and methods
US6845495B2 (en) 2001-12-20 2005-01-18 Lsi Logic Corporation Multidirectional router
JP3631464B2 (ja) * 2001-12-27 2005-03-23 株式会社東芝 半導体装置
JP2003197792A (ja) 2001-12-28 2003-07-11 Sanyo Electric Co Ltd 半導体装置
KR100422393B1 (ko) * 2002-01-17 2004-03-11 한국전자통신연구원 격자형 표류 영역 구조를 갖는 이디모스 소자 및 그 제조방법
US6735110B1 (en) * 2002-04-17 2004-05-11 Xilinx, Inc. Memory cells enhanced for resistance to single event upset
US6724044B2 (en) * 2002-05-10 2004-04-20 General Semiconductor, Inc. MOSFET device having geometry that permits frequent body contact
US7363099B2 (en) 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
JP4282051B2 (ja) 2002-07-22 2009-06-17 シャープ株式会社 半導体集積回路製造用マスクパターンデータ生成方法およびその検証方法
US6772859B2 (en) 2002-09-26 2004-08-10 Rpg Diffusor Systems, Inc. Embodiments of aperiodic tiling of a single asymmetric diffusive base shape
US6744081B2 (en) 2002-10-30 2004-06-01 Lsi Logic Corporation Interleaved termination ring
US7334198B2 (en) 2002-12-31 2008-02-19 Transmeta Corporation Software controlled transistor body bias
US6936898B2 (en) * 2002-12-31 2005-08-30 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US7091574B2 (en) 2003-03-13 2006-08-15 International Business Machines Corporation Voltage island circuit placement
US7003748B1 (en) 2003-06-01 2006-02-21 Cadence Design Systems, Inc. Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring
US7049699B1 (en) 2003-11-12 2006-05-23 Transmeta Corporation Low RC structures for routing body-bias voltage
US7049652B2 (en) 2003-12-10 2006-05-23 Sandisk Corporation Pillar cell flash memory technology
US7012461B1 (en) * 2003-12-23 2006-03-14 Transmeta Corporation Stabilization component for a substrate potential regulation circuit
US7015741B2 (en) 2003-12-23 2006-03-21 Intel Corporation Adaptive body bias for clock skew compensation
US7859062B1 (en) * 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7388260B1 (en) 2004-03-31 2008-06-17 Transmeta Corporation Structure for spanning gap in body-bias voltage routing structure
US7174526B2 (en) 2004-07-30 2007-02-06 Lsi Logic Corporation Accurate density calculation with density views in layout databases
US7598573B2 (en) * 2004-11-16 2009-10-06 Robert Paul Masleid Systems and methods for voltage distribution via multiple epitaxial layers
US7302661B2 (en) 2005-06-14 2007-11-27 International Business Machines Corporation Efficient electromagnetic modeling of irregular metal planes
US7788613B2 (en) 2005-07-06 2010-08-31 Fujitsu Limited Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture

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