JP2006114768A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
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- 238000002513 implantation Methods 0.000 claims description 42
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 29
- 229910052814 silicon oxide Inorganic materials 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
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- 238000005468 ion implantation Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910001416 lithium ion Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- -1 Ta 2 O 3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Abstract
【解決手段】 ゲート電極のドレイン電極24側の端部15aの近傍からドレイン電極24の方向(X2方向)に形成された第1ドレイン領域21と、第1ドレイン領域21の内側でドレイン電極24に接するドレインコンタクト領域23と、ドレインコンタクト領域23の周囲および下側に形成された第2ドレイン領域22とから構成し、第2ドレイン領域22の不純物濃度を第1ドレイン領域21よりも高濃度でかつドレインコンタクト領域23よりも低濃度に設定する。さらに、第2ドレイン領域22をそのゲート電極15側の端部22aがゲート電極の端部15aから所定の距離L1だけ離間した配置とする。
【選択図】 図2
Description
図2は、本発明の第1の実施の形態に係る半導体装置の断面図である。図3は、第1の実施の形態に係る半導体装置の平面図である。なお、図3では、素子分離領域、コンタクト、およびゲート絶縁膜は説明の便宜のため省略して示している。ここでは、nチャネルMOSトランジスタを例に説明する。
図9は、本発明の第2の実施の形態に係る半導体装置の断面図である。図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
図10は、本発明の第3の実施の形態に係る半導体装置の断面図である。図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
(付記1) 第1の導電型の半導体基板と、
前記半導体基板の表面にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極の一端の近傍に設けられた前記第1の導電型とは反対導電型の第2の導電型の第1のドレイン領域と、
前記第1のドレイン領域内に設けられ、第1のドレイン領域の不純物濃度よりも高濃度の第2の導電型のドレインコンタクト領域と、
前記ドレインコンタクト領域の周囲および下側に設けられた第2の導電型の第2のドレイン領域とを備え、
前記第2のドレイン領域は、
不純物濃度がドレインコンタクト領域よりも低濃度であり、かつ第1のドレイン領域よりも高濃度であり、
ゲート電極側の端部がゲート電極の前記一端から所定の距離を離間して設けられてなることを特徴とする半導体装置。
(付記2) 前記第2のドレイン領域は、底部が第1のドレイン領域の底部よりも深く設けられてなることを特徴とする付記1記載の半導体装置。
(付記3) 第1の導電型の半導体基板と、
前記半導体基板の表面にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極の一端の近傍に設けられた前記第1の導電型とは反対導電型の第2の導電型の第1のドレイン領域と、
前記第1のドレイン領域内に設けられ、第1のドレイン領域の不純物濃度よりも高濃度の第2の導電型のドレインコンタクト領域と、
前記ドレインコンタクト領域の周囲および下側に設けられた第2の導電型の第2のドレイン領域とを備え、
前記第2のドレイン領域は、
不純物濃度がドレインコンタクト領域よりも低濃度であり、かつ第1のドレイン領域と略同等であり、
底部が前記第1のドレイン領域の底部よりも深く、
ゲート電極側の端部がゲート電極の前記一端から所定の距離を離間して設けられてなることを特徴とする半導体装置。
(付記4) 第2のドレイン領域は、不純物がドレインコンタクト領域の不純物と同等かあるいは該ドレインコンタクト領域の不純物よりも拡散係数が大きい不純物からなることを特徴とする付記1〜3のうち、いずれか一項記載の半導体装置。
(付記5) 当該半導体装置はnチャネルMOSトランジスタであり、
前記第1のドレイン領域および第2のドレイン領域の不純物はPまたはAsからなり、
前記ドレインコンタクト領域の不純物がAsからなることを特徴とする付記1〜4のうち、いずれか一項記載の半導体装置。
(付記6) 前記所定の距離は、0.5μm〜5μmの範囲に設定されてなることを特徴とする付記1〜5のうち、いずれか一項記載の半導体装置。
(付記7) 前記第2のドレイン領域のゲート電極側の端部と、ドレインコンタクト領域ゲート電極側の端部との距離は、第2のドレイン領域の底部の深さと略同等かそれよりも大きいことを特徴とする付記1〜6のうち、いずれか一項記載の半導体装置。
(付記8) 前記第2のドレイン領域は、前記第1のドレイン領域よりもゲート幅方向に延在して形成されてなることを特徴とする付記1〜7のうち、いずれか一項記載の半導体装置。
(付記9) 前記ゲート電極のゲート長方向の長さが0.6μm〜5.0μmの範囲に設定されることを特徴とする付記1〜8のうち、いずれか一項記載の半導体装置。
(付記10) 第1の導電型の半導体基板と、
前記半導体基板の表面にゲート絶縁膜および該ゲート絶縁膜に連続して設けられたフィールド酸化膜と、
前記ゲート絶縁膜およびフィールド酸化膜上に延在して設けられたゲート電極と、
前記ゲート電極のゲート絶縁膜とフィールド酸化膜との境界部の近傍に設けられた前記第1の導電型とは反対導電型の第2の導電型の第1のドレイン領域と、
前記第1のドレイン領域内に設けられ、第1のドレイン領域の不純物濃度よりも高濃度の第2の導電型のドレインコンタクト領域と、
前記ドレインコンタクト領域の周囲および下側に設けられた第2の導電型の第2のドレイン領域とを備え、
前記第2のドレイン領域は、
不純物濃度がドレインコンタクト領域よりも低濃度であり、かつ第1のドレイン領域よりも高濃度であり、
ゲート電極側の端部がゲート電極の前記境界部から所定の距離を離間して設けられてなることを特徴とする半導体装置。
(付記11) 前記所定の距離は0.5μm〜5μmの範囲に設定されてなることを特徴とする付記10記載の半導体装置。
(付記12) 付記1〜11のうち、いずれか一項記載の半導体装置と、
バイポーラトランジスタとを備える半導体装置。
(付記13) 第1の導電型の半導体基板上にゲート絶縁膜およびゲート電極を形成する工程と、
前記ゲート電極の一端の近傍の半導体基板に前記第1の導電型とは反対導電型の第2の導電型の第1の不純物を第1の注入量で注入し第1のドレイン領域を形成する工程と、
前記第1のドレイン領域の略内側に第2の導電型の第2の不純物を第1の注入量よりも多い第2の注入量を注入して第2のドレイン領域を形成する工程と、
前記第2のドレイン領域の内側に第2の導電型の第3の不純物を第2の注入量よりも多い第3の注入量を注入してドレインコンタクト領域を形成する工程とを含み、
前記第2のドレイン領域を形成する工程は、前記ゲート電極の前記一端から所定の距離を離間して第2の不純物を注入することを特徴とする半導体装置の製造方法。
(付記14) 前記第2のドレイン領域を形成する工程は、前記第1の不純物を注入する際の注入エネルギーよりも大きな注入エネルギーで第2の不純物を注入することを特徴とする付記13記載の半導体装置の製造方法。
(付記15) 第1の導電型の半導体基板上にゲート絶縁膜およびゲート電極を形成する工程と、
前記ゲート電極の一端の近傍の半導体基板に前記第1の導電型とは反対導電型の第2の導電型の第1の不純物を第1の注入量で注入し第1のドレイン領域を形成する工程と、
前記第1のドレイン領域の略内側に第2の導電型の第2の不純物を第1の注入量と略同量で、かつ前記第1の不純物を注入する際の注入エネルギーよりも大きな注入エネルギーで注入して第2のドレイン領域を形成する工程と、
前記第2のドレイン領域の内側に第2の導電型の第3の不純物を第2の注入量よりも多い第3の注入量を注入してドレインコンタクト領域を形成する工程とを含み、
前記第2のドレイン領域を形成する工程は、前記ゲート電極の前記一端から所定の距離を離間して第2の不純物を注入することを特徴とする半導体装置の製造方法。
(付記16) 前記第1の不純物と第2の不純物は、同一の不純物であり、前記第3の不純物よりも前記半導体基板中の拡散係数が大きいことを特徴とする付記13〜15のうち、いずれか一項記載の半導体装置の製造方法。
11 シリコン基板
12 素子分離領域
13 p型ウェル領域
14 シリコン酸化膜
15 ゲート電極
16 ソース領域
18、24 コンタクト
20 ドレイン領域
21 第1ドレイン領域
22 第2ドレイン領域
23 ドレインコンタクト領域
31、32、33 レジスト膜
60 npn形バイポーラトランジスタ
70 nチャネルMOSトランジスタ
80 pチャネルMOSトランジスタ
Claims (8)
- 第1の導電型の半導体基板と、
前記半導体基板の表面にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極の一端の近傍に設けられた前記第1の導電型とは反対導電型の第2の導電型の第1のドレイン領域と、
前記第1のドレイン領域内に設けられ、第1のドレイン領域の不純物濃度よりも高濃度の第2の導電型のドレインコンタクト領域と、
前記ドレインコンタクト領域の周囲および下側に設けられた第2の導電型の第2のドレイン領域とを備え、
前記第2のドレイン領域は、
不純物濃度がドレインコンタクト領域よりも低濃度であり、かつ第1のドレイン領域よりも高濃度であり、
ゲート電極側の端部がゲート電極の前記一端から所定の距離を離間して設けられてなることを特徴とする半導体装置。 - 前記第2のドレイン領域は、底部が第1のドレイン領域の底部よりも深く設けられてなることを特徴とする請求項1記載の半導体装置。
- 第1の導電型の半導体基板と、
前記半導体基板の表面にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極の一端の近傍に設けられた前記第1の導電型とは反対導電型の第2の導電型の第1のドレイン領域と、
前記第1のドレイン領域内に設けられ、第1のドレイン領域の不純物濃度よりも高濃度の第2の導電型のドレインコンタクト領域と、
前記ドレインコンタクト領域の周囲および下側に設けられた第2の導電型の第2のドレイン領域とを備え、
前記第2のドレイン領域は、
不純物濃度がドレインコンタクト領域よりも低濃度であり、かつ第1のドレイン領域と略同等であり、
底部が前記第1のドレイン領域の底部よりも深く、
ゲート電極側の端部がゲート電極の前記一端から所定の距離を離間して設けられてなることを特徴とする半導体装置。 - 第2のドレイン領域は、不純物がドレインコンタクト領域の不純物と同等かあるいは該ドレインコンタクト領域の不純物よりも前記半導体基板中の拡散係数が大きい不純物からなることを特徴とする請求項1〜3のうち、いずれか一項記載の半導体装置。
- 前記所定の距離は、0.5μm〜5μmの範囲に設定されてなることを特徴とする請求項1〜4のうち、いずれか一項記載の半導体装置。
- 第1の導電型の半導体基板上にゲート絶縁膜およびゲート電極を形成する工程と、
前記ゲート電極の一端の近傍の半導体基板に前記第1の導電型とは反対導電型の第2の導電型の第1の不純物を第1の注入量で注入し第1のドレイン領域を形成する工程と、
前記第1のドレイン領域の略内側に第2の導電型の第2の不純物を第1の注入量よりも多い第2の注入量を注入して第2のドレイン領域を形成する工程と、
前記第2のドレイン領域の内側に第2の導電型の第3の不純物を第2の注入量よりも多い第3の注入量を注入してドレインコンタクト領域を形成する工程とを含み、
前記第2のドレイン領域を形成する工程は、前記ゲート電極の前記一端から所定の距離を離間して第2の不純物を注入することを特徴とする半導体装置の製造方法。 - 前記第2のドレイン領域を形成する工程は、前記第1の不純物を注入する際の注入エネルギーよりも大きな注入エネルギーで第2の不純物を注入することを特徴とする請求項6記載の半導体装置の製造方法。
- 第1の導電型の半導体基板上にゲート絶縁膜およびゲート電極を形成する工程と、
前記ゲート電極の一端の近傍の半導体基板に前記第1の導電型とは反対導電型の第2の導電型の第1の不純物を第1の注入量で注入し第1のドレイン領域を形成する工程と、
前記第1のドレイン領域の略内側に第2の導電型の第2の不純物を第1の注入量と略同量で、かつ前記第1の不純物を注入する際の注入エネルギーよりも大きな注入エネルギーで注入して第2のドレイン領域を形成する工程と、
前記第2のドレイン領域の内側に第2の導電型の第3の不純物を第2の注入量よりも多い第3の注入量を注入してドレインコンタクト領域を形成する工程とを含み、
前記第2のドレイン領域を形成する工程は、前記ゲート電極の前記一端から所定の距離を離間して第2の不純物を注入することを特徴とする半導体装置の製造方法。
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TW094106782A TWI257649B (en) | 2004-10-15 | 2005-03-07 | Semiconductor device and manufacturing method of the same |
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JP2008098624A (ja) * | 2006-09-15 | 2008-04-24 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US7723748B2 (en) | 2007-10-02 | 2010-05-25 | Ricoh Company, Ltd. | Semiconductor device including electrostatic discharge protection circuit |
JP2012114209A (ja) * | 2010-11-24 | 2012-06-14 | On Semiconductor Trading Ltd | 半導体装置及びその製造方法 |
US8735997B2 (en) | 2006-09-15 | 2014-05-27 | Semiconductor Components Industries, Llc | Semiconductor device having drain/source surrounded by impurity layer and manufacturing method thereof |
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JP2009231811A (ja) * | 2008-02-27 | 2009-10-08 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
US8643101B2 (en) | 2011-04-20 | 2014-02-04 | United Microelectronics Corp. | High voltage metal oxide semiconductor device having a multi-segment isolation structure |
US8501603B2 (en) | 2011-06-15 | 2013-08-06 | United Microelectronics Corp. | Method for fabricating high voltage transistor |
US20130043513A1 (en) | 2011-08-19 | 2013-02-21 | United Microelectronics Corporation | Shallow trench isolation structure and fabricating method thereof |
JP6723775B2 (ja) * | 2016-03-16 | 2020-07-15 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
TWI744133B (zh) | 2019-12-18 | 2021-10-21 | 台灣積體電路製造股份有限公司 | 具有改善的靜電放電保護的半導體元件及其形成方法 |
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CN1761071A (zh) | 2006-04-19 |
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US20110076821A1 (en) | 2011-03-31 |
JP5114824B2 (ja) | 2013-01-09 |
CN100424888C (zh) | 2008-10-08 |
US8298898B2 (en) | 2012-10-30 |
TWI257649B (en) | 2006-07-01 |
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US20060081924A1 (en) | 2006-04-20 |
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