US20130043513A1 - Shallow trench isolation structure and fabricating method thereof - Google Patents

Shallow trench isolation structure and fabricating method thereof Download PDF

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US20130043513A1
US20130043513A1 US13/213,211 US201113213211A US2013043513A1 US 20130043513 A1 US20130043513 A1 US 20130043513A1 US 201113213211 A US201113213211 A US 201113213211A US 2013043513 A1 US2013043513 A1 US 2013043513A1
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shallow trench
high voltage
substrate
isolation structure
device area
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US13/213,211
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Liang-An HUANG
Yu-Chun Huang
Chin-Fu Lin
Yu-Ciao Lin
Yu-Chieh Lin
Hsin-Liang Liu
Chun-hung Cheng
Yuan-Cheng Yang
Yau-Kae Sheu
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US13/213,211 priority Critical patent/US20130043513A1/en
Assigned to UNITED MICROELECTRONICS CORPORATION reassignment UNITED MICROELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, CHUN-HUNG, HUANG, LIANG-AN, HUANG, YU-CHUN, LIN, CHIN-FU, LIN, YU-CHIEH, LIN, YU-CIAO, LIU, HSIN-LIANG, SHEU, YAU-KAE, YANG, Yuan-cheng
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a shallow trench isolation structure and a fabricating method thereof, and more particularly to a shallow trench isolation structure and a fabricating method of a shallow trench isolation structure in the manufacture of a semiconductor device.
  • BACKGROUND OF THE INVENTION
  • Nowadays, in the mainstream of integrated circuit production, a low voltage logic circuit and a high voltage semiconductor device are implemented on the same integrated circuit chip. For providing effective isolation between adjacent electronic components, in the low voltage logic circuit and a high voltage semiconductor device, an isolation structure is usually formed in the integrated circuit chip to separate adjacent electronic components from each other. As known, a shallow trench isolation (STI) structure is one of the most popular isolation structures. Moreover, the shallow trench isolation structures of the low voltage logic circuit and the high voltage semiconductor device are simultaneously produced in the same fabricating process.
  • As the device size of the low voltage logic circuit is gradually developed toward miniaturization because of the process progress, the width and the depth of the shallow trench isolation structure are reduced. If the dimension of the shallow trench isolation structure of the high voltage semiconductor device is identical to the dimension of the shallow trench isolation structure of the low voltage logic circuit, the isolation efficacy of the high voltage semiconductor device is unsatisfied. Therefore, there is a need of providing an improved fabricating method of a shallow trench isolation structure.
  • SUMMARY OF THE INVENTION
  • Therefore, the object of the present invention is to provide a fabricating method of a shallow trench isolation structure in order to achieve effective isolation.
  • In accordance with an aspect, the present invention provides a fabricating method of a shallow trench isolation structure. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.
  • In an embodiment, a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process. The first shallow trench is deeper than the second shallow trench.
  • In an embodiment, an inclination angle of a sidewall of the preliminary shallow trench is from 105 to 135 degrees, so that the first shallow trench has a shoulder part with a gentle slope.
  • In an embodiment, after the first shallow trench isolation structure is formed, the fabricating method further includes the following steps. A pre-clean process is performed to treat the shallow trench isolation structure, so that a top surface of the shallow trench isolation structure is shrunk to a location below the shoulder part. Then, a high voltage gate dielectric layer is formed on the shallow trench isolation structure and a surface of the substrate.
  • In an embodiment, after the preliminary shallow trench is formed, the fabricating method further includes a step of forming a spacer on a sidewall of the preliminary shallow trench, wherein the spacer is made of the same material as the dielectric material.
  • In an embodiment, after the preliminary shallow trench is formed and before the second etching process is done, the fabricating method further includes a step of performing an ion implantation process to dope the high voltage device area of the substrate with a dopant, so that a high voltage well region is formed in the high voltage device area.
  • In an embodiment, the step of filling the dielectric material in the first shallow trench includes sub-steps of performing a high density plasma chemical vapor deposition process to deposit the dielectric material, and performing a chemical mechanical polishing process to flatten the dielectric material.
  • In accordance with another aspect, the present invention provides a shallow trench isolation structure. The shallow trench isolation structure includes a substrate, a first shallow trench and a dielectric material layer. A high voltage device area is defined in the substrate. The first shallow trench is formed in the high voltage device area. The first shallow trench has an upper portion and a lower portion. A sidewall of the upper portion has a shoulder part with a gentle slope. The dielectric material layer is filled within the first shallow trench to a level near the shoulder part.
  • In an embodiment, a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process. The first shallow trench is deeper than the second shallow trench.
  • In an embodiment, an inclination angle of the shoulder part is from 105 to 135 degrees.
  • In an embodiment, the substrate is a silicon substrate, the dielectric material is silicon oxide, and the high voltage gate dielectric layer is made of silicon dioxide.
  • In accordance with a further aspect, the present invention provides a high voltage metal-oxide-semiconductor field-effect transistor. The high voltage metal-oxide-semiconductor field-effect transistor includes a substrate, a channel region, at least one shallow trench and a dielectric material layer. The channel region is formed in the substrate. The shallow trench is located at a side of the channel region. The shallow trench has an upper portion and a lower portion. A sidewall of the upper portion has a shoulder part with a gentle slope. The dielectric material layer is filled within the first shallow trench to a level near the shoulder part.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
  • FIGS. 1A˜1J are schematic cross-sectional views illustrating a process of fabricating a shallow trench isolation (STI) structure according to an embodiment of the present invention; and
  • FIG. 2 is a schematic cross-sectional view illustrating a symmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention; and
  • FIG. 3 is a schematic cross-sectional view illustrating an asymmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
  • FIGS. 1A˜1J are schematic cross-sectional views illustrating a process of fabricating a shallow trench isolation (STI) structure according to an embodiment of the present invention.
  • Firstly, as shown in FIG. 1A, a silicon substrate 1 is provided. A pad oxide layer 10 is formed on a surface of the silicon substrate 1. In addition, the silicon substrate 1 is divided into two areas, i.e. a high voltage device area 11 and a low voltage device area 12.
  • Then, a zero-etch process is performed by using a photolithography and etching process to define an alignment mark (not shown) on the silicon substrate 1. Especially, for performing the zero-etch process, a pattern for defining a shallow trench isolation structure of the high voltage device area 11 should be previously created in the photo mask. After the zero-etch process is performed, a preliminary shallow trench 110 is formed in the high voltage device area 11 (see FIG. 1B). The preliminary shallow trench 110 has a first depth. Since the device density of the high voltage device area 11 is relatively lower, there is a sufficient space for providing a tapered preliminary shallow trench 110. That is, the sidewall of the preliminary shallow trench 110 is not upright. By adjusting the etching conditions, the sidewall of the preliminary shallow trench 110 has a gentle slope. In an embodiment, the sidewall of the preliminary shallow trench 110 has an inclination angle in a range from 105 to 135 degrees.
  • Then, as shown in FIG. 1 C, an ion implantation process (as is indicated by the arrow) is performed to dope the high voltage device area 11 with a dopant. Consequently, a high voltage well region 119 is formed in the high voltage device area 11.
  • Then, as shown in FIG. 1D, a spacer 111 is formed on the sidewall of the preliminary shallow trench 110. For example, the spacer 111 is made of silicon oxide. In this embodiment, an anisotropic etching process is performed to remove the excess silicon oxide and the pad oxide layer 10 while remaining the spacer 111. By the spacer 111, the possibility of forming a residual (e.g. silicon nitride) on the sidewall of the preliminary shallow trench 110 in the subsequent process will be minimized. In other words, the spacer 111 is effective to improve the profile of the isolation structure in the subsequent process.
  • Then, as shown in FIG. 1E, a pad oxide layer 13 and a silicon nitride layer 14 are sequentially formed on the surface of the silicon substrate 1.
  • Then, a shallow trench etching process is performed to simultaneously form first shallow trenches 15 and second shallow trenches 16 in the high voltage device area 11 and the low voltage device area 12, respectively. The depth of the first shallow trench 15 in the high voltage device area 11 is greater than the depth of the second shallow trench 16 in the second trench 16 (see FIG. 1F). Since the preliminary shallow trench 110 formed by the zero-etch process contributes to an upper portion of the first shallow trench 15, the first shallow trench 15 with the upper portion and a lower portion becomes deeper than the second shallow trench 16. Under this circumstance, the isolation efficacy is enhanced. In other words, the depth of the first shallow trench 15 can be adjusted through the preliminary shallow trench 110. Since the method of the present invention is capable of adjusting the depth of the shallow trench in the high voltage device area, the conventional problem will be obviated.
  • However, a defect is possibly formed on the silicon substrate 1 after the shallow trench etching process is performed. For repairing the defect, the silicon substrate having the shallow trenches may be treated by a high temperature furnace process (at about 100° C.). Consequently, a silicon oxide repair linear layer (not shown) is formed on the sidewalls of the shallow trenches for repairing the defect and rounding the shape corners. Under this circumstance, the electrical isolation efficacy is enhanced.
  • Then, a high density plasma chemical vapor deposition (HDP-CVD) process is performed, and thus a silicon oxide layer 17 is filled within the first shallow trenches 15 and second shallow trenches 16 and formed on the silicon nitride layer 14. Then, a chemical mechanical polishing process is performed to remove the silicon oxide layer 17 overlying the silicon nitride layer 14, the top surface of the silicon oxide layer 17 is substantially at the same level as the topside of the silicon nitride layer 14 (see FIG. 1G).
  • Then, as shown in FIG. 1H, an etch-back process and a nitride oxide removing process are performed to remove the silicon nitride layer 14. Consequently, shallow trench isolation structures 180 and 181 made of silicon oxide are formed and partially exposed. The shallow trench isolation structures 180 are located at the high voltage device area 11. The shallow trench isolation structures 181 are located at the low voltage device area 12. The shallow trench isolation structure 180 is deeper than the shallow trench isolation structure 181. Moreover, the shallow trench isolation structure 180 has a shoulder part 1801 with a gentle slope.
  • Then, as shown in FIG. 1I, another ion implantation process is performed to produce other parts of the high voltage device, for example the high voltage field (HV field) region (see FIG. 2).
  • Then, as shown in FIG. 1J, one or more pre-clean processes are performed to treat the shallow trench isolation structure 180. Inevitably, the shallow trench isolation structure 180 is shrunk from the top surface to a location at a level near the shoulder part 1801. Then, a thermal oxidation process is performed, and thus a high voltage gate dielectric layer 191 is grown on the surface of the substrate 1 and the shallow trench isolation structure 180. Then, a high voltage gate conductor layer 192 is formed on the top surfaces of the high voltage gate dielectric layer 191 and the shallow trench isolation structure 180. In this embodiment, the high voltage gate dielectric layer 191 is produced by a high temperature furnace oxidation process. Moreover, the high voltage gate dielectric layer 191 is made of the same material as the shallow trench isolation structure 180. For example, the high voltage gate dielectric layer 191 is made of silicon oxide. Since the shallow trench isolation structure 180 has a shoulder part 1801 with a gentle slope, the thickness of the high voltage gate dielectric layer 191 over the shallow trench isolation structure 180 is distributed more uniformly. For example, the thickness dl of the high voltage gate dielectric layer 191 overlying the channel region 199 is about 950 angstroms, and the thickness d2 of the high voltage gate dielectric layer 191 at the edge of the channel region 199 is about 700 angstroms. Since the ratio of d2 to d1 is maintained at a ratio greater than 0.7, the high voltage device area has enhanced insulation efficacy and is suitable to be operated in the high voltage condition.
  • FIG. 2 is a schematic cross-sectional view illustrating a symmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention. Take NMOS as an example. As shown in FIG. 2, a high voltage P-well region 20 is formed in a substrate 2. A high voltage N-field region 24 and a high voltage P-field region 25 are formed in the high voltage P-well region 20. A heavily P-doped region 220 and a heavily N-doped region 210 are formed served as a body contact region and a source/drain region, respectively. Moreover, the shallow trench isolation structures 200, 201 and 202 are produced by the fabricating method of the present invention. Consequently, the metal-oxide-semiconductor field-effect transistor has enhanced insulation efficacy and is suitable to be operated in the high voltage condition. Moreover, since the thickness distribution of the high voltage gate dielectric layer 21 is more uniform, if only the single-side shoulder parts 2000 and 2010 of the shallow trench isolation structures 200 and 201 in the channel region 23 under the high voltage gate dielectric layer 21 and the high voltage gate conductor layer 192 are created, the above benefits are also achievable. Of course, if all of the shallow trench isolation structures have the shoulder parts, the benefits will become more evident.
  • FIG. 3 is a schematic cross-sectional view illustrating an asymmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention. In comparison with the symmetric metal-oxide-semiconductor field-effect transistor of FIG. 2, the shallow trench isolation structures 201, 202, the high voltage N-field region 24, the high voltage P-field region 25 and the heavily P-doped region 220 are not included in a side of the asymmetric metal-oxide-semiconductor field-effect transistor of FIG. 3. That is, only the heavily N-doped region 210 serving as the source/drain contact region and the outermost shallow trench isolation structure 30 are retained.
  • While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (16)

1. A fabricating method of a shallow trench isolation structure, the fabricating method comprising steps of:
providing a substrate, wherein a high voltage device area is defined in the substrate;
performing a first etching process to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area;
performing a second etching process to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area; and
filling a dielectric material in the first shallow trench, thereby forming a first shallow trench isolation structure.
2. The fabricating method according to claim 1, wherein a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process, wherein the first shallow trench is deeper than the second shallow trench.
3. The fabricating method according to claim 1, wherein an inclination angle of a sidewall of the preliminary shallow trench is from 105 to 135 degrees, so that the first shallow trench has a shoulder part with a gentle slope.
4. The fabricating method according to claim 3, wherein after the first shallow trench isolation structure is formed, the fabricating method further comprises steps of:
performing a pre-clean process to treat the shallow trench isolation structure, so that a top surface of the shallow trench isolation structure is shrunk to a location below the shoulder part; and
forming a high voltage gate dielectric layer on the shallow trench isolation structure and a surface of the substrate.
5. The fabricating method according to claim 1, wherein after the preliminary shallow trench is formed, the fabricating method further comprises a step of forming a spacer on a sidewall of the preliminary shallow trench, wherein the spacer is made of the same material as the dielectric material.
6. The fabricating method according to claim 1, wherein after the preliminary shallow trench is formed and before the second etching process is done, the fabricating method further comprises a step of performing an ion implantation process to dope the high voltage device area of the substrate with a dopant, so that a high voltage well region is formed in the high voltage device area.
7. The fabricating method according to claim 1, wherein the step of filling the dielectric material in the first shallow trench comprises sub-steps of:
performing a high density plasma chemical vapor deposition process to deposit the dielectric material; and
performing a chemical mechanical polishing process to flatten the dielectric material.
8. A shallow trench isolation structure, comprising:
a substrate, wherein a high voltage device area is defined in the substrate;
a first shallow trench formed in the high voltage device area, wherein the first shallow trench has an upper portion and a lower portion, and a sidewall of the upper portion has a shoulder part with a gentle slope; and
a dielectric material layer filled within the first shallow trench to a level near the shoulder part.
9. The shallow trench isolation structure according to claim 8, wherein a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process, wherein the first shallow trench is deeper than the second shallow trench.
10. The shallow trench isolation structure according to claim 8, wherein an inclination angle of the shoulder part is from 105 to 135 degrees.
11. The shallow trench isolation structure according to claim 8, wherein the substrate is a silicon substrate, and the dielectric material layer is made of silicon oxide.
12. The shallow trench isolation structure according to claim 8, further comprising:
a high voltage gate dielectric layer formed on a surface of the substrate and in contact with the dielectric material layer; and
a high voltage gate conductor layer formed on the top surfaces of the high voltage gate dielectric layer and the dielectric material layer.
13. A high voltage metal-oxide-semiconductor field-effect transistor, comprising:
a substrate;
a channel region formed in the substrate;
at least one shallow trench located at a side of the channel region, wherein the shallow trench has an upper portion and a lower portion, and a sidewall of the upper portion has a shoulder part with a gentle slope; and
a dielectric material layer filled within the first shallow trench to a level near the shoulder part.
14. The high voltage metal-oxide-semiconductor field-effect transistor according to claim 13, wherein an inclination angle of the shoulder part is from 105 to 135 degrees.
15. The high voltage metal-oxide-semiconductor field-effect transistor according to claim 13, wherein the substrate is a silicon substrate, and the dielectric material layer is made of silicon oxide.
16. The high voltage metal-oxide-semiconductor field-effect transistor according to claim 13, further comprising:
a high voltage gate dielectric layer formed on a surface of the substrate and in contact with the dielectric material layer; and
a high voltage gate conductor layer formed on the top surfaces of the high voltage gate dielectric layer and the dielectric material layer.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140339636A1 (en) * 2013-05-16 2014-11-20 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US20160099183A1 (en) * 2013-10-07 2016-04-07 Stmicroelectronics (Crolles 2) Sas Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuit
US9368570B2 (en) * 2014-07-01 2016-06-14 Novatek Microelectronics Corp. Integrated circuit of driving device with different operating voltages
TWI577020B (en) * 2013-05-15 2017-04-01 聯華電子股份有限公司 High voltage metal-oxide-semiconductor transistor device
US20170323897A1 (en) * 2015-04-28 2017-11-09 SK Hynix Inc. Manufacturing method of semiconductor device
US20180166545A1 (en) * 2016-12-08 2018-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with capping structure and method of forming the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110299398A (en) * 2018-03-22 2019-10-01 联华电子股份有限公司 High voltage transistor and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180490B1 (en) * 1999-05-25 2001-01-30 Chartered Semiconductor Manufacturing Ltd. Method of filling shallow trenches

Family Cites Families (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344081A (en) 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
US4396999A (en) 1981-06-30 1983-08-02 International Business Machines Corporation Tunneling transistor memory cell
US4893160A (en) 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4918333A (en) 1988-10-31 1990-04-17 Anderson Floyd E Microprocessor having high current drive
US4958089A (en) 1988-12-20 1990-09-18 Gazelle Microcircuits, Inc. High output drive FET buffer for providing high initial current to a subsequent stage
US5070381A (en) 1990-03-20 1991-12-03 Texas Instruments Incorporated High voltage lateral transistor
US5040045A (en) 1990-05-17 1991-08-13 U.S. Philips Corporation High voltage MOS transistor having shielded crossover path for a high voltage connection bus
US5268589A (en) 1990-09-28 1993-12-07 Siemens Aktiengesellschaft Semiconductor chip having at least one electrical resistor means
US5296393A (en) 1990-11-23 1994-03-22 Texas Instruments Incorporated Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods
IT1254799B (en) 1992-02-18 1995-10-11 St Microelectronics Srl A VDMOS transistor with improved voltage withstand characteristics.
US5346835A (en) 1992-07-06 1994-09-13 Texas Instruments Incorporated Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method
US5539238A (en) 1992-09-02 1996-07-23 Texas Instruments Incorporated Area efficient high voltage Mosfets with vertical resurf drift regions
JP3203814B2 (en) 1992-10-19 2001-08-27 富士電機株式会社 Semiconductor device
US5326711A (en) 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5585294A (en) 1994-10-14 1996-12-17 Texas Instruments Incorporated Method of fabricating lateral double diffused MOS (LDMOS) transistors
US5534721A (en) 1994-11-30 1996-07-09 At&T Corp. Area-efficient layout for high voltage lateral devices
US5939763A (en) 1996-09-05 1999-08-17 Advanced Micro Devices, Inc. Ultrathin oxynitride structure and process for VLSI applications
US6624495B2 (en) 1997-04-23 2003-09-23 Altera Corporation Adjustable threshold isolation transistor
US5783476A (en) 1997-06-26 1998-07-21 Siemens Aktiengesellschaft Integrated circuit devices including shallow trench isolation
US6002156A (en) 1997-09-16 1999-12-14 Winbond Electronics Corp. Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering
US5998301A (en) 1997-12-18 1999-12-07 Advanced Micro Devices, Inc. Method and system for providing tapered shallow trench isolation structure profile
TW400614B (en) 1998-11-06 2000-08-01 United Microelectronics Corp The manufacture method of Shallow Trench Isolation(STI)
US5950090A (en) 1998-11-16 1999-09-07 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor
GB9826291D0 (en) 1998-12-02 1999-01-20 Koninkl Philips Electronics Nv Field-effect semi-conductor devices
US6424005B1 (en) 1998-12-03 2002-07-23 Texas Instruments Incorporated LDMOS power device with oversized dwell
JP3955404B2 (en) * 1998-12-28 2007-08-08 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6165846A (en) 1999-03-02 2000-12-26 Zilog, Inc. Method of eliminating gate leakage in nitrogen annealed oxides
US6066884A (en) 1999-03-19 2000-05-23 Lucent Technologies Inc. Schottky diode guard ring structures
US6265752B1 (en) 1999-05-25 2001-07-24 Taiwan Semiconductor Manufacturing, Co., Inc. Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same
US6277757B1 (en) 1999-06-01 2001-08-21 Winbond Electronics Corp. Methods to modify wet by dry etched via profile
US6627949B2 (en) 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
JP2001015741A (en) 1999-06-30 2001-01-19 Toshiba Corp Field effect transistor
JP3442009B2 (en) 1999-09-24 2003-09-02 松下電器産業株式会社 Structure of the high-voltage mos transistor
US6277675B1 (en) 1999-10-28 2001-08-21 United Microelectronics Corp. Method of fabricating high voltage MOS device
US6144538A (en) 1999-12-20 2000-11-07 United Microelectronics Corp. High voltage MOS transistor used in protection circuits
JP4200626B2 (en) 2000-02-28 2008-12-24 株式会社デンソー Method for manufacturing insulated gate type power device
US6326283B1 (en) 2000-03-07 2001-12-04 Vlsi Technology, Inc. Trench-diffusion corner rounding in a shallow-trench (STI) process
US6391729B1 (en) * 2000-03-09 2002-05-21 Advanced Micro Devices, Inc. Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding
US6297108B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Method of forming a high voltage MOS transistor on a semiconductor wafer
US6351017B1 (en) 2000-03-22 2002-02-26 Advanced Micro Devices, Inc. High voltage transistor with modified field implant mask
TW441074B (en) 2000-04-15 2001-06-16 United Microelectronics Corp Electrostatic discharge protection circuit structure for high voltage device
JP4696335B2 (en) 2000-05-30 2011-06-08 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2002026328A (en) 2000-07-04 2002-01-25 Toshiba Corp Horizontal semiconductor device
US6306700B1 (en) 2000-08-07 2001-10-23 United Microelectronics Corp. Method for forming high voltage devices compatible with low voltages devices on semiconductor substrate
US6593620B1 (en) 2000-10-06 2003-07-15 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
EP1338032A2 (en) 2000-10-30 2003-08-27 Advanced Micro Devices Inc. Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell
US7075575B2 (en) 2000-11-06 2006-07-11 Isetex, Inc. Gated vertical punch through device used as a high performance charge detection amplifier
JP2002237591A (en) 2000-12-31 2002-08-23 Texas Instruments Inc Dmos transistor source structure and method for manufacturing the same
US6894349B2 (en) 2001-06-08 2005-05-17 Intersil Americas Inc. Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
KR100387531B1 (en) 2001-07-30 2003-06-18 삼성전자주식회사 Method for fabricating semiconductor device
US6846729B2 (en) 2001-10-01 2005-01-25 International Rectifier Corporation Process for counter doping N-type silicon in Schottky device Ti silicide barrier
KR100418435B1 (en) 2001-12-26 2004-02-14 한국전자통신연구원 Method for fabricating a power integrated circuit device
KR100456691B1 (en) 2002-03-05 2004-11-10 삼성전자주식회사 Semiconductor device having dual isolation structure and method of fabricating the same
US6833602B1 (en) 2002-09-06 2004-12-21 Lattice Semiconductor Corporation Device having electrically isolated low voltage and high voltage regions and process for fabricating the device
US6791155B1 (en) 2002-09-20 2004-09-14 Integrated Device Technology, Inc. Stress-relieved shallow trench isolation (STI) structure and method for forming the same
KR100487412B1 (en) 2002-09-24 2005-05-03 매그나칩 반도체 유한회사 Method for fabricating of semiconductor device
TW578321B (en) 2002-10-02 2004-03-01 Topro Technology Inc Complementary metal-oxide semiconductor structure for a battery protection circuit and battery protection circuit therewith
US20040070050A1 (en) 2002-10-10 2004-04-15 Taiwan Semiconductor Manufacturing Company Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through the field penetration effect
US7041572B2 (en) 2002-10-25 2006-05-09 Vanguard International Semiconductor Corporation Fabrication method for a deep trench isolation structure of a high-voltage device
KR100440263B1 (en) 2002-10-29 2004-07-15 주식회사 하이닉스반도체 Transistor in a semiconductor device and a method of manufacturing the same
US6819184B2 (en) 2002-11-06 2004-11-16 Cree Microwave, Inc. RF transistor amplifier linearity using suppressed third order transconductance
US7019377B2 (en) 2002-12-17 2006-03-28 Micrel, Inc. Integrated circuit including high voltage devices and low voltage devices
US6764890B1 (en) 2003-01-29 2004-07-20 Cypress Semiconductor Corporation Method of adjusting the threshold voltage of a mosfet
KR100554830B1 (en) 2003-06-05 2006-02-22 주식회사 하이닉스반도체 Method of manufacturing a flash memory device
KR100493061B1 (en) 2003-06-20 2005-06-02 삼성전자주식회사 Single chip data processing device having embeded nonvolatile memory
US7023050B2 (en) 2003-07-11 2006-04-04 Salama C Andre T Super junction / resurf LDMOST (SJR-LDMOST)
US6825531B1 (en) 2003-07-11 2004-11-30 Micrel, Incorporated Lateral DMOS transistor with a self-aligned drain region
US7525150B2 (en) 2004-04-07 2009-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage double diffused drain MOS transistor with medium operation voltage
US7129559B2 (en) 2004-04-09 2006-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage semiconductor device utilizing a deep trench structure
US7358567B2 (en) 2004-06-07 2008-04-15 United Microelectronics Corp. High-voltage MOS device and fabrication thereof
US7148540B2 (en) 2004-06-28 2006-12-12 Agere Systems Inc. Graded conductive structure for use in a metal-oxide-semiconductor device
US7125777B2 (en) 2004-07-15 2006-10-24 Fairchild Semiconductor Corporation Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
JP4947931B2 (en) 2004-08-12 2012-06-06 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5114824B2 (en) 2004-10-15 2013-01-09 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
WO2006053055A2 (en) 2004-11-09 2006-05-18 Fultec Semiconductor Inc. High-voltage transistor fabrication with trench etching technique
US7091079B2 (en) 2004-11-11 2006-08-15 United Microelectronics Corp. Method of forming devices having three different operation voltages
US20060138085A1 (en) 2004-12-23 2006-06-29 Chun-Hsien Chien Plasma etching method with reduced particles production
KR100697283B1 (en) * 2005-03-29 2007-03-20 삼성전자주식회사 Device isolation structure of the semiconductor device and method of forming the same
US7368785B2 (en) 2005-05-25 2008-05-06 United Microelectronics Corp. MOS transistor device structure combining Si-trench and field plate structures for high voltage device
US7067365B1 (en) 2005-05-26 2006-06-27 United Microelectronics Corp. High-voltage metal-oxide-semiconductor devices and method of making the same
US7244975B2 (en) 2005-07-05 2007-07-17 United Microelectronics Corp. High-voltage device structure
US7868394B2 (en) 2005-08-09 2011-01-11 United Microelectronics Corp. Metal-oxide-semiconductor transistor and method of manufacturing the same
US7477532B2 (en) 2005-08-18 2009-01-13 Semiconductor Components Industries, L.L.C. Method of forming a start-up device and structure therefor
US7485925B2 (en) 2005-08-30 2009-02-03 United Microelectronics Corp. High voltage metal oxide semiconductor transistor and fabricating method thereof
JP2007134674A (en) 2005-10-11 2007-05-31 Elpida Memory Inc Semiconductor device and its manufacturing method
US7309636B2 (en) 2005-11-07 2007-12-18 United Microelectronics Corp. High-voltage metal-oxide-semiconductor device and method of manufacturing the same
CN100461375C (en) 2005-12-05 2009-02-11 中芯国际集成电路制造(上海)有限公司 Method for making isolation structure for flash-memory semiconductor device
US7372104B2 (en) 2005-12-12 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage CMOS devices
KR100734302B1 (en) 2006-01-12 2007-06-26 삼성전자주식회사 Semiconductor integrated circuit device for increasing integration density and fabrication method thereof
US20080185629A1 (en) 2007-02-01 2008-08-07 Denso Corporation Semiconductor device having variable operating information
US20070273001A1 (en) 2006-05-24 2007-11-29 Jung-Ching Chen System on chip and method for manufacturing the same
US20080160706A1 (en) 2006-12-27 2008-07-03 Jin Hyo Jung Method for fabricating semiconductor device
US7763928B2 (en) 2007-05-31 2010-07-27 United Microelectronics Corp. Multi-time programmable memory
US20080308868A1 (en) 2007-06-15 2008-12-18 United Microelectronics Corp. High voltage metal oxide semiconductor transistor and fabrication method thereof
US20090014810A1 (en) * 2007-06-26 2009-01-15 Eun-Jong Shin Method for fabricating shallow trench isolation and method for fabricating transistor
US20100213517A1 (en) 2007-10-19 2010-08-26 Nxp B.V. High voltage semiconductor device
US7741659B2 (en) 2007-10-25 2010-06-22 United Microelectronics Corp. Semiconductor device
US20090111252A1 (en) 2007-10-30 2009-04-30 United Microelectronics Corp. Method for forming deep well region of high voltage device
US20090159966A1 (en) 2007-12-20 2009-06-25 Chih-Jen Huang High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate
US8324705B2 (en) 2008-05-27 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Schottky diodes having low-voltage and high-concentration rings
KR100974697B1 (en) 2008-07-09 2010-08-06 주식회사 동부하이텍 Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device
US7906810B2 (en) 2008-08-06 2011-03-15 United Microelectronics Corp. LDMOS device for ESD protection circuit
US7982288B2 (en) 2008-10-17 2011-07-19 United Microelectronics Corp. Semiconductor device and method of fabricating the same
US7902600B2 (en) 2008-12-11 2011-03-08 United Microelectronics Corp. Metal oxide semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180490B1 (en) * 1999-05-25 2001-01-30 Chartered Semiconductor Manufacturing Ltd. Method of filling shallow trenches

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI577020B (en) * 2013-05-15 2017-04-01 聯華電子股份有限公司 High voltage metal-oxide-semiconductor transistor device
US20140339636A1 (en) * 2013-05-16 2014-11-20 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US8921972B2 (en) * 2013-05-16 2014-12-30 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US20160099183A1 (en) * 2013-10-07 2016-04-07 Stmicroelectronics (Crolles 2) Sas Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuit
US9368570B2 (en) * 2014-07-01 2016-06-14 Novatek Microelectronics Corp. Integrated circuit of driving device with different operating voltages
US20170323897A1 (en) * 2015-04-28 2017-11-09 SK Hynix Inc. Manufacturing method of semiconductor device
US20180166545A1 (en) * 2016-12-08 2018-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with capping structure and method of forming the same
US10157990B2 (en) * 2016-12-08 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with capping structure and method of forming the same

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