JP2006041354A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2006041354A
JP2006041354A JP2004221764A JP2004221764A JP2006041354A JP 2006041354 A JP2006041354 A JP 2006041354A JP 2004221764 A JP2004221764 A JP 2004221764A JP 2004221764 A JP2004221764 A JP 2004221764A JP 2006041354 A JP2006041354 A JP 2006041354A
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Japan
Prior art keywords
gate
field effect
cross
gate electrode
effect transistor
Prior art date
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Pending
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JP2004221764A
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English (en)
Japanese (ja)
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JP2006041354A5 (enExample
Inventor
Masaru Hisamoto
大 久本
Kan Yasui
感 安井
Shinichiro Kimura
紳一郎 木村
Tetsuya Ishimaru
哲也 石丸
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Renesas Technology Corp
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Renesas Technology Corp
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Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004221764A priority Critical patent/JP2006041354A/ja
Priority to TW094120881A priority patent/TWI360865B/zh
Priority to US11/182,013 priority patent/US7504689B2/en
Priority to KR1020050064173A priority patent/KR20060050209A/ko
Priority to CN200510086030XA priority patent/CN1728401B/zh
Publication of JP2006041354A publication Critical patent/JP2006041354A/ja
Publication of JP2006041354A5 publication Critical patent/JP2006041354A5/ja
Priority to US12/368,538 priority patent/US7847343B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
JP2004221764A 2004-07-29 2004-07-29 半導体装置及びその製造方法 Pending JP2006041354A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2004221764A JP2006041354A (ja) 2004-07-29 2004-07-29 半導体装置及びその製造方法
TW094120881A TWI360865B (en) 2004-07-29 2005-06-22 Semiconductor device and manufacturing method of s
US11/182,013 US7504689B2 (en) 2004-07-29 2005-07-15 Semiconductor device and manufacturing method of semiconductor device
KR1020050064173A KR20060050209A (ko) 2004-07-29 2005-07-15 반도체장치 및 그 제조방법
CN200510086030XA CN1728401B (zh) 2004-07-29 2005-07-20 半导体器件及其制造方法
US12/368,538 US7847343B2 (en) 2004-07-29 2009-02-10 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004221764A JP2006041354A (ja) 2004-07-29 2004-07-29 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2006041354A true JP2006041354A (ja) 2006-02-09
JP2006041354A5 JP2006041354A5 (enExample) 2007-04-05

Family

ID=35731149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004221764A Pending JP2006041354A (ja) 2004-07-29 2004-07-29 半導体装置及びその製造方法

Country Status (5)

Country Link
US (2) US7504689B2 (enExample)
JP (1) JP2006041354A (enExample)
KR (1) KR20060050209A (enExample)
CN (1) CN1728401B (enExample)
TW (1) TWI360865B (enExample)

Cited By (34)

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JP2007281091A (ja) * 2006-04-04 2007-10-25 Renesas Technology Corp 半導体装置およびその製造方法
JP2008263034A (ja) * 2007-04-11 2008-10-30 Oki Electric Ind Co Ltd 半導体記憶装置の製造方法
JP2009049097A (ja) * 2007-08-16 2009-03-05 Oki Electric Ind Co Ltd 半導体不揮発性メモリセルとその製造方法、及びその半導体不揮発性メモリセルを有する半導体不揮発性メモリとその製造方法
JP2011049580A (ja) * 2010-10-18 2011-03-10 Renesas Electronics Corp 半導体装置
JP2011119331A (ja) * 2009-12-01 2011-06-16 Renesas Electronics Corp 半導体集積回路装置の製造方法
US8154075B2 (en) 2009-02-03 2012-04-10 Renesas Electronics Corporation Nonvolatile semiconductor memory device and method for manufacturing the same
JP2014017343A (ja) * 2012-07-09 2014-01-30 Renesas Electronics Corp 半導体装置及びその製造方法
JP2016004822A (ja) * 2014-06-13 2016-01-12 ルネサスエレクトロニクス株式会社 半導体装置
JP2016507908A (ja) * 2013-03-14 2016-03-10 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 増大したチャネル領域有効幅を有する不揮発性メモリセル及びその製造方法
JP2016051738A (ja) * 2014-08-28 2016-04-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR20170026172A (ko) 2015-08-26 2017-03-08 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
KR20170034345A (ko) 2015-09-18 2017-03-28 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
JP2017112331A (ja) * 2015-12-18 2017-06-22 株式会社フローディア メモリセル、不揮発性半導体記憶装置、および不揮発性半導体記憶装置の製造方法
EP3188216A1 (en) 2015-12-28 2017-07-05 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US9741869B1 (en) 2016-02-24 2017-08-22 Renesas Electronics Corporation Semiconductor device and method for manufacturing same
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US9899403B2 (en) 2016-06-14 2018-02-20 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
KR20180035129A (ko) 2016-09-28 2018-04-05 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
JP2018056378A (ja) * 2016-09-29 2018-04-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10056402B2 (en) 2016-09-30 2018-08-21 Renesas Electronics Corporation Semiconductor device
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CN109119423A (zh) * 2017-06-22 2019-01-01 瑞萨电子株式会社 半导体装置及其制造方法
US10217759B2 (en) 2016-09-30 2019-02-26 Renesas Electronics Corporation Semiconductor device
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US10424591B2 (en) 2017-09-19 2019-09-24 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US10546946B2 (en) 2016-02-24 2020-01-28 Renesas Electronics Corporation Method for manufacturing semiconductor device having thinned fins
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JP4601316B2 (ja) * 2004-03-31 2010-12-22 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
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WO2008075656A1 (ja) * 2006-12-19 2008-06-26 Nec Corporation 半導体装置
JP5404149B2 (ja) * 2009-04-16 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置
US8598646B2 (en) * 2011-01-13 2013-12-03 Spansion Llc Non-volatile FINFET memory array and manufacturing method thereof
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JP2014232810A (ja) * 2013-05-29 2014-12-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
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JP2018107317A (ja) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
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Cited By (63)

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JP2007281091A (ja) * 2006-04-04 2007-10-25 Renesas Technology Corp 半導体装置およびその製造方法
US8530958B2 (en) 2006-04-04 2013-09-10 Renesas Electronics Corporation Semiconductor device having split gate type, non-volatile memory cells and a method of manufacturing the same
JP2008263034A (ja) * 2007-04-11 2008-10-30 Oki Electric Ind Co Ltd 半導体記憶装置の製造方法
JP2009049097A (ja) * 2007-08-16 2009-03-05 Oki Electric Ind Co Ltd 半導体不揮発性メモリセルとその製造方法、及びその半導体不揮発性メモリセルを有する半導体不揮発性メモリとその製造方法
US8154075B2 (en) 2009-02-03 2012-04-10 Renesas Electronics Corporation Nonvolatile semiconductor memory device and method for manufacturing the same
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