JP2005347636A - トレンチ・アイソレーション構造の形成方法 - Google Patents

トレンチ・アイソレーション構造の形成方法 Download PDF

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Publication number
JP2005347636A
JP2005347636A JP2004167435A JP2004167435A JP2005347636A JP 2005347636 A JP2005347636 A JP 2005347636A JP 2004167435 A JP2004167435 A JP 2004167435A JP 2004167435 A JP2004167435 A JP 2004167435A JP 2005347636 A JP2005347636 A JP 2005347636A
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JP
Japan
Prior art keywords
film
substrate
silicon
silicon nitride
nitride liner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004167435A
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English (en)
Japanese (ja)
Other versions
JP2005347636A5 (enExample
Inventor
Teruno Nagura
倉 映 乃 名
Yasuo Shimizu
水 泰 雄 清
Masaaki Ichiyama
山 昌 章 一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AZ Electronic Materials Japan Co Ltd
Original Assignee
AZ Electronic Materials Japan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AZ Electronic Materials Japan Co Ltd filed Critical AZ Electronic Materials Japan Co Ltd
Priority to JP2004167435A priority Critical patent/JP2005347636A/ja
Priority to PCT/JP2005/009891 priority patent/WO2005119758A1/ja
Priority to KR1020077000156A priority patent/KR20070028518A/ko
Priority to EP05743708.9A priority patent/EP1768175B1/en
Priority to CNA200580017325XA priority patent/CN1965402A/zh
Priority to US11/596,785 priority patent/US20080061398A1/en
Priority to TW094118295A priority patent/TW200625520A/zh
Publication of JP2005347636A publication Critical patent/JP2005347636A/ja
Publication of JP2005347636A5 publication Critical patent/JP2005347636A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
JP2004167435A 2004-06-04 2004-06-04 トレンチ・アイソレーション構造の形成方法 Pending JP2005347636A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2004167435A JP2005347636A (ja) 2004-06-04 2004-06-04 トレンチ・アイソレーション構造の形成方法
PCT/JP2005/009891 WO2005119758A1 (ja) 2004-06-04 2005-05-30 トレンチ・アイソレーション構造の形成方法
KR1020077000156A KR20070028518A (ko) 2004-06-04 2005-05-30 트렌치ㆍ아이솔레이션 구조의 형성방법
EP05743708.9A EP1768175B1 (en) 2004-06-04 2005-05-30 Method for forming trench isolation structure
CNA200580017325XA CN1965402A (zh) 2004-06-04 2005-05-30 用于形成沟槽隔离结构的方法
US11/596,785 US20080061398A1 (en) 2004-06-04 2005-05-30 Method for forming trench isolation structure
TW094118295A TW200625520A (en) 2004-06-04 2005-06-03 Method for forming trench isolation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004167435A JP2005347636A (ja) 2004-06-04 2004-06-04 トレンチ・アイソレーション構造の形成方法

Publications (2)

Publication Number Publication Date
JP2005347636A true JP2005347636A (ja) 2005-12-15
JP2005347636A5 JP2005347636A5 (enExample) 2007-06-14

Family

ID=35463125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004167435A Pending JP2005347636A (ja) 2004-06-04 2004-06-04 トレンチ・アイソレーション構造の形成方法

Country Status (7)

Country Link
US (1) US20080061398A1 (enExample)
EP (1) EP1768175B1 (enExample)
JP (1) JP2005347636A (enExample)
KR (1) KR20070028518A (enExample)
CN (1) CN1965402A (enExample)
TW (1) TW200625520A (enExample)
WO (1) WO2005119758A1 (enExample)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194286A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 半導体装置の製造方法
WO2008035820A1 (en) * 2006-09-21 2008-03-27 Jsr Corporation Silicone resin composition and method for forming trench isolation
JP2008101206A (ja) * 2006-09-21 2008-05-01 Jsr Corp シリコーン樹脂、シリコーン樹脂組成物およびトレンチアイソレーションの形成方法
JP2008140896A (ja) * 2006-11-30 2008-06-19 Tokyo Electron Ltd 熱処理方法、熱処理装置及び記憶媒体
JP2008266119A (ja) * 2006-11-24 2008-11-06 Jsr Corp シリコーン樹脂、シリコーン樹脂組成物およびトレンチアイソレーションの形成方法
JPWO2009096603A1 (ja) * 2008-02-01 2011-05-26 Jsr株式会社 トレンチアイソレーションの形成方法
JP2012049509A (ja) * 2010-07-29 2012-03-08 Tokyo Electron Ltd トレンチの埋め込み方法および成膜システム
US8154102B2 (en) 2008-12-16 2012-04-10 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
JP2012138501A (ja) * 2010-12-27 2012-07-19 Tokyo Electron Ltd トレンチの埋め込み方法および成膜装置
JP2017216335A (ja) * 2016-05-31 2017-12-07 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、およびプログラム
KR20200042009A (ko) * 2017-09-12 2020-04-22 어플라이드 머티어리얼스, 인코포레이티드 보호 배리어 층을 사용하여 반도체 구조들을 제조하기 위한 장치 및 방법들

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JP2009044000A (ja) * 2007-08-09 2009-02-26 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
US7999355B2 (en) 2008-07-11 2011-08-16 Air Products And Chemicals, Inc. Aminosilanes for shallow trench isolation films
KR101683071B1 (ko) 2010-09-08 2016-12-06 삼성전자 주식회사 반도체 소자 및 그 제조방법
KR101361454B1 (ko) * 2012-08-23 2014-02-21 이근수 반도체 소자의 실리콘 산화막 형성 방법
CN103531522B (zh) * 2013-10-30 2016-08-17 上海华力微电子有限公司 浅沟槽隔离结构制备方法
KR101825546B1 (ko) * 2014-05-26 2018-02-05 제일모직 주식회사 실리카계 막 형성용 조성물, 및 실리카계 막의 제조방법
US10020185B2 (en) 2014-10-07 2018-07-10 Samsung Sdi Co., Ltd. Composition for forming silica layer, silica layer, and electronic device
KR101837971B1 (ko) 2014-12-19 2018-03-13 삼성에스디아이 주식회사 실리카계 막 형성용　조성물, 실리카계 막, 및 전자 디바이스
KR101833800B1 (ko) 2014-12-19 2018-03-02 삼성에스디아이 주식회사 실리카계 막 형성용 조성물, 실리카계 막의 제조방법 및 상기 실리카계 막을 포함하는 전자 소자
CN106356281B (zh) * 2015-07-16 2019-10-25 中芯国际集成电路制造(上海)有限公司 二氧化硅介电薄膜制备方法
KR20170014946A (ko) 2015-07-31 2017-02-08 삼성에스디아이 주식회사 실리카 막 형성용 조성물, 실리카 막의 제조방법 및 실리카 막
CN107393864A (zh) * 2017-08-29 2017-11-24 睿力集成电路有限公司 一种隔离结构及其制造方法
CN110739264B (zh) * 2019-10-30 2022-08-09 上海华力微电子有限公司 浅沟槽隔离结构及其形成方法、半导体器件的制作方法

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Publication number Priority date Publication date Assignee Title
JPH0897277A (ja) * 1994-09-29 1996-04-12 Toshiba Corp 半導体装置の製造方法
JPH10303289A (ja) * 1997-04-30 1998-11-13 Hitachi Ltd 半導体集積回路装置の製造方法
JPH11307626A (ja) * 1998-04-27 1999-11-05 Nec Corp トレンチ・アイソレーション構造の形成方法
JP2001308090A (ja) * 2000-04-25 2001-11-02 Tonengeneral Sekiyu Kk 微細溝をシリカ質材料で埋封する方法及びシリカ質膜付き基材
JP2002043408A (ja) * 2000-07-28 2002-02-08 Nec Kansai Ltd 半導体装置の製造方法
JP2002088156A (ja) * 2000-09-07 2002-03-27 Dow Corning Corp 結晶性水素化シルセスキオキサンの製造方法
US20020168873A1 (en) * 2001-05-09 2002-11-14 Ahn Dong-Ho Method of forming a semiconductor device
JP2002367980A (ja) * 2001-06-07 2002-12-20 Samsung Electronics Co Ltd 半導体装置のシリコン酸化膜形成方法およびこれを用いた素子分離方法
JP2003031796A (ja) * 2001-07-11 2003-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004311487A (ja) * 2003-04-02 2004-11-04 Hitachi Ltd 半導体装置の製造方法

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KR100568100B1 (ko) * 2001-03-05 2006-04-05 삼성전자주식회사 트렌치형 소자 분리막 형성 방법
KR100512167B1 (ko) * 2001-03-12 2005-09-02 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 트렌치형 소자 분리막형성방법
US6767642B2 (en) * 2002-03-11 2004-07-27 E. I. Du Pont Nemours And Company Preparation and use of crosslinkable acrylosilane polymers containing vinyl silane monomers
JP2004273519A (ja) * 2003-03-05 2004-09-30 Clariant (Japan) Kk トレンチ・アイソレーション構造の形成方法
US7521378B2 (en) * 2004-07-01 2009-04-21 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897277A (ja) * 1994-09-29 1996-04-12 Toshiba Corp 半導体装置の製造方法
JPH10303289A (ja) * 1997-04-30 1998-11-13 Hitachi Ltd 半導体集積回路装置の製造方法
JPH11307626A (ja) * 1998-04-27 1999-11-05 Nec Corp トレンチ・アイソレーション構造の形成方法
JP2001308090A (ja) * 2000-04-25 2001-11-02 Tonengeneral Sekiyu Kk 微細溝をシリカ質材料で埋封する方法及びシリカ質膜付き基材
JP2002043408A (ja) * 2000-07-28 2002-02-08 Nec Kansai Ltd 半導体装置の製造方法
JP2002088156A (ja) * 2000-09-07 2002-03-27 Dow Corning Corp 結晶性水素化シルセスキオキサンの製造方法
US20020168873A1 (en) * 2001-05-09 2002-11-14 Ahn Dong-Ho Method of forming a semiconductor device
JP2002367980A (ja) * 2001-06-07 2002-12-20 Samsung Electronics Co Ltd 半導体装置のシリコン酸化膜形成方法およびこれを用いた素子分離方法
JP2003031796A (ja) * 2001-07-11 2003-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004311487A (ja) * 2003-04-02 2004-11-04 Hitachi Ltd 半導体装置の製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194286A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 半導体装置の製造方法
WO2008035820A1 (en) * 2006-09-21 2008-03-27 Jsr Corporation Silicone resin composition and method for forming trench isolation
JP2008101206A (ja) * 2006-09-21 2008-05-01 Jsr Corp シリコーン樹脂、シリコーン樹脂組成物およびトレンチアイソレーションの形成方法
JP2008266119A (ja) * 2006-11-24 2008-11-06 Jsr Corp シリコーン樹脂、シリコーン樹脂組成物およびトレンチアイソレーションの形成方法
KR101131640B1 (ko) 2006-11-30 2012-03-28 도쿄엘렉트론가부시키가이샤 폴리실라잔막의 처리 방법
JP2008140896A (ja) * 2006-11-30 2008-06-19 Tokyo Electron Ltd 熱処理方法、熱処理装置及び記憶媒体
JPWO2009096603A1 (ja) * 2008-02-01 2011-05-26 Jsr株式会社 トレンチアイソレーションの形成方法
US8154102B2 (en) 2008-12-16 2012-04-10 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
US8603892B2 (en) 2008-12-16 2013-12-10 Elpida Memory, Inc. Method of manufacturing a semiconductor device
JP2012049509A (ja) * 2010-07-29 2012-03-08 Tokyo Electron Ltd トレンチの埋め込み方法および成膜システム
JP2012138501A (ja) * 2010-12-27 2012-07-19 Tokyo Electron Ltd トレンチの埋め込み方法および成膜装置
JP2017216335A (ja) * 2016-05-31 2017-12-07 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、およびプログラム
KR20200042009A (ko) * 2017-09-12 2020-04-22 어플라이드 머티어리얼스, 인코포레이티드 보호 배리어 층을 사용하여 반도체 구조들을 제조하기 위한 장치 및 방법들
JP2020533803A (ja) * 2017-09-12 2020-11-19 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 保護バリア層を使用して半導体構造を製造する装置および方法
JP7274461B2 (ja) 2017-09-12 2023-05-16 アプライド マテリアルズ インコーポレイテッド 保護バリア層を使用して半導体構造を製造する装置および方法
KR102659317B1 (ko) * 2017-09-12 2024-04-18 어플라이드 머티어리얼스, 인코포레이티드 보호 배리어 층을 사용하여 반도체 구조들을 제조하기 위한 장치 및 방법들

Also Published As

Publication number Publication date
US20080061398A1 (en) 2008-03-13
CN1965402A (zh) 2007-05-16
EP1768175A8 (en) 2007-05-09
KR20070028518A (ko) 2007-03-12
WO2005119758A1 (ja) 2005-12-15
EP1768175B1 (en) 2019-05-15
TW200625520A (en) 2006-07-16
EP1768175A4 (en) 2011-07-27
EP1768175A1 (en) 2007-03-28

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