JP2005210114A5 - - Google Patents

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Publication number
JP2005210114A5
JP2005210114A5 JP2005006181A JP2005006181A JP2005210114A5 JP 2005210114 A5 JP2005210114 A5 JP 2005210114A5 JP 2005006181 A JP2005006181 A JP 2005006181A JP 2005006181 A JP2005006181 A JP 2005006181A JP 2005210114 A5 JP2005210114 A5 JP 2005210114A5
Authority
JP
Japan
Prior art keywords
integrated circuit
transistors
contact portion
planar metal
power transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005006181A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005210114A (ja
JP4596925B2 (ja
Filing date
Publication date
Priority claimed from US10/765,474 external-priority patent/US7265448B2/en
Application filed filed Critical
Publication of JP2005210114A publication Critical patent/JP2005210114A/ja
Publication of JP2005210114A5 publication Critical patent/JP2005210114A5/ja
Application granted granted Critical
Publication of JP4596925B2 publication Critical patent/JP4596925B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005006181A 2004-01-26 2005-01-13 集積回路および集積回路用の相互接続構造 Expired - Fee Related JP4596925B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/765,474 US7265448B2 (en) 2004-01-26 2004-01-26 Interconnect structure for power transistors

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2005276912A Division JP2006093712A (ja) 2004-01-26 2005-09-22 アルミニウム・コアを有する相互接続構造
JP2005276911A Division JP5502255B2 (ja) 2004-01-26 2005-09-22 集積回路を接続するための相互接続構造

Publications (3)

Publication Number Publication Date
JP2005210114A JP2005210114A (ja) 2005-08-04
JP2005210114A5 true JP2005210114A5 (enExample) 2005-11-17
JP4596925B2 JP4596925B2 (ja) 2010-12-15

Family

ID=34750426

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2005006181A Expired - Fee Related JP4596925B2 (ja) 2004-01-26 2005-01-13 集積回路および集積回路用の相互接続構造
JP2005276912A Pending JP2006093712A (ja) 2004-01-26 2005-09-22 アルミニウム・コアを有する相互接続構造
JP2005276911A Expired - Lifetime JP5502255B2 (ja) 2004-01-26 2005-09-22 集積回路を接続するための相互接続構造

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2005276912A Pending JP2006093712A (ja) 2004-01-26 2005-09-22 アルミニウム・コアを有する相互接続構造
JP2005276911A Expired - Lifetime JP5502255B2 (ja) 2004-01-26 2005-09-22 集積回路を接続するための相互接続構造

Country Status (5)

Country Link
US (2) US7265448B2 (enExample)
EP (3) EP1727200B1 (enExample)
JP (3) JP4596925B2 (enExample)
CN (3) CN1805137A (enExample)
TW (3) TWI354368B (enExample)

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TWI469292B (zh) * 2011-07-26 2015-01-11 萬國半導體股份有限公司 應用雙層引線框架的堆疊式功率半導體裝置及其製備方法
US8853860B2 (en) * 2012-03-23 2014-10-07 Teledyne Scientific & Imaging, Llc Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance
US8759956B2 (en) * 2012-07-05 2014-06-24 Infineon Technologies Ag Chip package and method of manufacturing the same
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US9960231B2 (en) * 2016-06-17 2018-05-01 Qualcomm Incorporated Standard cell architecture for parasitic resistance reduction
JP6658441B2 (ja) * 2016-10-06 2020-03-04 三菱電機株式会社 半導体装置
US10283526B2 (en) * 2016-12-21 2019-05-07 Qualcomm Incorporated Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop
US10236886B2 (en) 2016-12-28 2019-03-19 Qualcomm Incorporated Multiple via structure for high performance standard cells
US10249711B2 (en) * 2017-06-29 2019-04-02 Teledyne Scientific & Imaging, Llc FET with micro-scale device array
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US11508659B2 (en) * 2020-09-10 2022-11-22 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure in semiconductor device and method of forming the same
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