JP2005191240A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2005191240A
JP2005191240A JP2003430092A JP2003430092A JP2005191240A JP 2005191240 A JP2005191240 A JP 2005191240A JP 2003430092 A JP2003430092 A JP 2003430092A JP 2003430092 A JP2003430092 A JP 2003430092A JP 2005191240 A JP2005191240 A JP 2005191240A
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JP
Japan
Prior art keywords
lead
semiconductor device
sealing body
resin sealing
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003430092A
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English (en)
Japanese (ja)
Other versions
JP2005191240A5 (https=
Inventor
Nagahiro Fukaya
修大 深谷
Toshiyuki Shintani
俊幸 新谷
Hajime Hasebe
一 長谷部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2003430092A priority Critical patent/JP2005191240A/ja
Priority to TW93135256A priority patent/TW200522328A/zh
Priority to US11/002,804 priority patent/US7410834B2/en
Priority to KR1020040109225A priority patent/KR20050065340A/ko
Priority to CNA2004101048856A priority patent/CN1638111A/zh
Publication of JP2005191240A publication Critical patent/JP2005191240A/ja
Publication of JP2005191240A5 publication Critical patent/JP2005191240A5/ja
Priority to US12/169,921 priority patent/US20080268576A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2003430092A 2003-12-25 2003-12-25 半導体装置及びその製造方法 Pending JP2005191240A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2003430092A JP2005191240A (ja) 2003-12-25 2003-12-25 半導体装置及びその製造方法
TW93135256A TW200522328A (en) 2003-12-25 2004-11-17 Semiconductor device and manufacturing method thereof
US11/002,804 US7410834B2 (en) 2003-12-25 2004-12-03 Method of manufacturing a semiconductor device
KR1020040109225A KR20050065340A (ko) 2003-12-25 2004-12-21 반도체장치 및 그 제조방법
CNA2004101048856A CN1638111A (zh) 2003-12-25 2004-12-24 半导体元件的制造方法
US12/169,921 US20080268576A1 (en) 2003-12-25 2008-07-09 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003430092A JP2005191240A (ja) 2003-12-25 2003-12-25 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2005191240A true JP2005191240A (ja) 2005-07-14
JP2005191240A5 JP2005191240A5 (https=) 2007-02-15

Family

ID=34697596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003430092A Pending JP2005191240A (ja) 2003-12-25 2003-12-25 半導体装置及びその製造方法

Country Status (5)

Country Link
US (2) US7410834B2 (https=)
JP (1) JP2005191240A (https=)
KR (1) KR20050065340A (https=)
CN (1) CN1638111A (https=)
TW (1) TW200522328A (https=)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311137A (ja) * 2004-04-22 2005-11-04 Sony Corp 半導体装置及びその製造方法、半導体装置の実装構造並びにリードフレーム
WO2007083490A1 (ja) * 2006-01-23 2007-07-26 Towa Corporation 電子部品の樹脂封止成形方法、ならびに、それに用いられる型組品およびリードフレーム
JP2008016469A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置
JP2008108872A (ja) * 2006-10-25 2008-05-08 Denso Corp モールドパッケージおよびその製造方法
JP2008186891A (ja) * 2007-01-29 2008-08-14 Denso Corp モールドパッケージおよびその製造方法ならびにモールドパッケージの実装構造
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP2014067750A (ja) * 2012-09-24 2014-04-17 Seiko Instruments Inc 樹脂封止型半導体装置およびその製造方法
JP2018074067A (ja) * 2016-11-01 2018-05-10 旭化成エレクトロニクス株式会社 半導体装置
JP2018200994A (ja) * 2017-05-29 2018-12-20 大口マテリアル株式会社 リードフレーム及びその製造方法
JP2019047061A (ja) * 2017-09-06 2019-03-22 大日本印刷株式会社 半導体装置およびその製造方法
JP2020038914A (ja) * 2018-09-05 2020-03-12 ローム株式会社 半導体装置
CN111463139A (zh) * 2016-03-03 2020-07-28 英飞凌科技股份有限公司 制造具有光学检测特征的模制的半导体封装体的方法
KR20210123752A (ko) * 2020-04-06 2021-10-14 (주)포시스 반도체 패키지용 리드프레임의 리드 구조 및 그 리드 가공 방법
WO2022209819A1 (ja) * 2021-04-01 2022-10-06 ローム株式会社 半導体装置および半導体装置の製造方法

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US8330270B1 (en) * 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
JP2008218811A (ja) 2007-03-06 2008-09-18 Hitachi Metals Ltd 機能素子パッケージ
US8120152B2 (en) 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5549066B2 (ja) * 2008-09-30 2014-07-16 凸版印刷株式会社 リードフレーム型基板とその製造方法、及び半導体装置
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
JP2010238693A (ja) * 2009-03-30 2010-10-21 Toppan Printing Co Ltd 半導体素子用基板の製造方法および半導体装置
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
JP5448727B2 (ja) * 2009-11-05 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
ITMI20120710A1 (it) * 2012-04-27 2013-10-28 St Microelectronics Srl Metodo per fabbricare dispositivi elettronici
US8841758B2 (en) * 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US8716066B2 (en) 2012-07-31 2014-05-06 Freescale Semiconductor, Inc. Method for plating a semiconductor package lead
US8890301B2 (en) 2012-08-01 2014-11-18 Analog Devices, Inc. Packaging and methods for packaging
US9070669B2 (en) 2012-11-09 2015-06-30 Freescale Semiconductor, Inc. Wettable lead ends on a flat-pack no-lead microelectronic package
US8535982B1 (en) 2012-11-29 2013-09-17 Freescale Semiconductor, Inc. Providing an automatic optical inspection feature for solder joints on semiconductor packages
KR101504897B1 (ko) * 2013-02-22 2015-03-23 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9190606B2 (en) * 2013-03-15 2015-11-17 Allegro Micosystems, LLC Packaging for an electronic device
US10345343B2 (en) 2013-03-15 2019-07-09 Allegro Microsystems, Llc Current sensor isolation
US20140299978A1 (en) * 2013-04-03 2014-10-09 Lingsen Precision Industries, Ltd. Quad flat non-lead package
US20140357022A1 (en) * 2013-06-04 2014-12-04 Cambridge Silicon Radio Limited A qfn with wettable flank
US9947636B2 (en) * 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
US20160148877A1 (en) * 2014-11-20 2016-05-26 Microchip Technology Incorporated Qfn package with improved contact pins
CN105895611B (zh) * 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
JP6577857B2 (ja) 2015-12-21 2019-09-18 ルネサスエレクトロニクス株式会社 半導体装置
CN105470231A (zh) * 2015-12-25 2016-04-06 华天科技（西安）有限公司 一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法
US10388616B2 (en) 2016-05-02 2019-08-20 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP6752639B2 (ja) 2016-05-02 2020-09-09 ローム株式会社 半導体装置の製造方法
US9847283B1 (en) 2016-11-06 2017-12-19 Nexperia B.V. Semiconductor device with wettable corner leads
US10199312B1 (en) 2017-09-09 2019-02-05 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US11227810B2 (en) * 2017-11-10 2022-01-18 Shindengen Electric Manufacturing Co., Ltd. Electronic module with a groove and press hole on the surface of a conductor
JP7037368B2 (ja) * 2018-01-09 2022-03-16 ローム株式会社 半導体装置および半導体装置の製造方法
JP7144157B2 (ja) * 2018-03-08 2022-09-29 エイブリック株式会社 半導体装置およびその製造方法
US11600557B2 (en) * 2018-08-21 2023-03-07 Texas Instruments Incorporated Packaged device having selective lead pullback for dimple depth control
CN109243988A (zh) * 2018-09-14 2019-01-18 上海凯虹科技电子有限公司 封装体及其封装方法
JP6827495B2 (ja) * 2019-05-16 2021-02-10 Ｔｏｗａ株式会社 半導体装置の製造方法
CN111668184B (zh) * 2020-07-14 2022-02-01 甬矽电子(宁波)股份有限公司 引线框制作方法和引线框结构
US11768230B1 (en) 2022-03-30 2023-09-26 Allegro Microsystems, Llc Current sensor integrated circuit with a dual gauge lead frame
TWI847658B (zh) * 2023-04-24 2024-07-01 強茂股份有限公司 具表面散熱結構的側面可濕潤半導體封裝元件及製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196005A (ja) * 1998-12-24 2000-07-14 Nec Corp 半導体装置
JP2000294719A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299400A (ja) 1999-04-14 2000-10-24 Sony Corp ノンリード・フラットパッケージ型半導体装置
JP3878781B2 (ja) * 1999-12-27 2007-02-07 株式会社ルネサステクノロジ 半導体装置の製造方法
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196005A (ja) * 1998-12-24 2000-07-14 Nec Corp 半導体装置
JP2000294719A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311137A (ja) * 2004-04-22 2005-11-04 Sony Corp 半導体装置及びその製造方法、半導体装置の実装構造並びにリードフレーム
WO2007083490A1 (ja) * 2006-01-23 2007-07-26 Towa Corporation 電子部品の樹脂封止成形方法、ならびに、それに用いられる型組品およびリードフレーム
JP2008016469A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置
JP2008108872A (ja) * 2006-10-25 2008-05-08 Denso Corp モールドパッケージおよびその製造方法
JP2008186891A (ja) * 2007-01-29 2008-08-14 Denso Corp モールドパッケージおよびその製造方法ならびにモールドパッケージの実装構造
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP2014067750A (ja) * 2012-09-24 2014-04-17 Seiko Instruments Inc 樹脂封止型半導体装置およびその製造方法
CN111463139A (zh) * 2016-03-03 2020-07-28 英飞凌科技股份有限公司 制造具有光学检测特征的模制的半导体封装体的方法
JP2018074067A (ja) * 2016-11-01 2018-05-10 旭化成エレクトロニクス株式会社 半導体装置
JP2018200994A (ja) * 2017-05-29 2018-12-20 大口マテリアル株式会社 リードフレーム及びその製造方法
JP2019047061A (ja) * 2017-09-06 2019-03-22 大日本印刷株式会社 半導体装置およびその製造方法
JP2020038914A (ja) * 2018-09-05 2020-03-12 ローム株式会社 半導体装置
JP7210868B2 (ja) 2018-09-05 2023-01-24 ローム株式会社 半導体装置
JP2023036823A (ja) * 2018-09-05 2023-03-14 ローム株式会社 半導体装置
US11894281B2 (en) 2018-09-05 2024-02-06 Rohm Co., Ltd. Semiconductor device including lead with varying thickness
JP7546034B2 (ja) 2018-09-05 2024-09-05 ローム株式会社 半導体装置
US12261094B2 (en) 2018-09-05 2025-03-25 Rohm Co., Ltd. Semiconductor device including lead with varying thickness
KR20210123752A (ko) * 2020-04-06 2021-10-14 (주)포시스 반도체 패키지용 리드프레임의 리드 구조 및 그 리드 가공 방법
KR102363175B1 (ko) * 2020-04-06 2022-02-15 (주)포시스 반도체 패키지용 리드프레임의 리드 구조 및 그 리드 가공 방법
WO2022209819A1 (ja) * 2021-04-01 2022-10-06 ローム株式会社 半導体装置および半導体装置の製造方法

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