JP2005135971A - 半導体集積回路の配線設計方法及び半導体集積回路 - Google Patents
半導体集積回路の配線設計方法及び半導体集積回路 Download PDFInfo
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
【解決手段】 予め規則性をもたせて配線パターンを形成した2つの基本配線パターン層と、それらの間に位置させる予め規則性をもたせてビアを形成した基本ビアアレイ層とに基づいて設計することにより、製造プロセス及び製品において作業の容易性及び信頼性を向上させる。
【選択図】 図15
Description
なお、一般に、半導体集積回路では、最下層を第1層と呼び、上方にいくに従って第2層、第3層、……と呼んでいるが、本件発明においては、説明の便宜上、最上層を第1層と呼び、下方に向かって第2層、第3層、……と呼ぶこととする。よって、例えば、“第2層”は上から数えて第2番目の層を指す。
本発明の実施形態の基本概念は以下の通りである。即ち、半導体装置の配線部分は階層的に複数の配線層(処理済配線層)から構成される。そして、これらの各処理済配線層は次のようにして構成される。つまり、各処理済配線層は、設計前の基本パターン(ストリップ状の配線パターン及び柱状のビア)が形成された基本配線層における配線パターン及びビアを、それぞれが必要とする密度となるように、カット(分離)や除去(消去)等する設計処理を施すことにより、得られる。つまり、基本配線層は、配線パターンの形成された基本配線パターン層と、ビアのアレイの形成されたビアアレイ層に分けられる。
先ず、レイアウトパターンと回路情報を入力する(S1)。つまり、回路情報の入力と、図1−図9に示す様な、規則的に配置された配線/ビアのレイアウトパターンを準備する。こちらは、配線層数とレイアウトエリアが決まれば、自動生成されることが望ましい。
次に、信号配線の経路を決定する(S2)。つまり、自動配線ツール等を用いて、回路情報や他の制約条件に基づき、信号配線の経路を決定する。
次に、配線及びビアの除去処理を行う(S3)。つまり、信号配線の経路が決定したら、自動配線ツール等により、不要なレイアウトパターンを部分的に取り除く処理を施す。これにより、信号配線としては用いられない配線及びビアの、不要な冗長レイアウトパターンが残る。
次に、残存させた冗長レイアウトパターン(配線及びビア)の残存と削除を判断し(S4)、不要と判断されたものは削除し(S5)、必要と判断されたものについては単位面積当りの密度調整を施し、均一化を図る(S6)。この後は、一般に行われるレイアウトパターンの検証工程を施す(S7)。
尚、上述した実施の形態は一例であって、本発明を限定するものではない。
2B,4B,6B ビア
1Aa、3Aa 信号用の配線パターン
1Ab,3Ab ダミー用のビア
2Ba 接続用のビア
2Bb ダミー用のビア
Claims (5)
- それぞれが、ストリップ状の複数の配線パターンを有し、互いに階層構造をなす、少なくとも2つの基本配線パターン層と、
これらの2つの基本配線パターン層の間に位置し、これらの2つの基本配線パターン層のそれぞれにおける前記配線パターン同士を中継接続するための複数のビアを有する、基本ビアアレイ層と、
前記2つの基本配線パターン層のうちの一方の側に位置し、この一方の基本配線パターン層における前記配線パターンの所期のものと、回路要素と、を接続するための複数のビアを有する他の基本ビアアレイ層と、
を配線設計の原資源として準備するに当り、
前記各基本配線パターン層を、自己の配線領域に、規則性をもった繰り返しパターンとして前記複数の配線パターンを、ある決められた一方向に走るものとして形成したものとして準備し、
前記基本ビアアレイ層を、自己の配線領域に、規則性をもった繰り返しパターンとして前記複数のビアをアレイ状に形成したものとして準備し、
前記各基本配線パターン層においては、前記複数の配線パターンのうちの所定のものを選択的に、信号用配線としての必要性及びダミー用配線の必要性から判断して、その途中の部分をカットすることにより分割して複数の配線パターン片とすることにより、設計処理済の処理済配線パターン層とすると共に、
前記基本ビア層においては、接続用ビアとしての必要性及びダミー用ビアとしての必要性から判断して、前記ビアのうちの不要なものを消去して、接続用ビアとダミー用ビアとするものを残存させて、設計処理済の処理済ビア層となし、
前記2つの処理済配線パターン層における前記配線パターン及び配線パターン片を前記処理済ビア層における残存する前記接続用ビアによって中継接続することにより所期の配線を形成すると共に、この配線に関与しない前記配線パターン及び配線パターン片並びに前記ダミー用ビアをダミーパターンとして残存させるようにしたことを特徴とする、半導体集積回路の配線設計方法。 - 前記配線に関与しない、前記配線パターンおよび配線パターン片を、ダミーパターンとして残存させるにあたり、残存させるものを選択することにより、ダミー配線の量及びパターンを所期のものとして、前記処理済み配線パターン全体の密度を調節するようにしたことを特徴とする請求項1に記載の半導体集積回路の配線設計方法。
- 階層構造において前記基本ビアアレイ層を挟んで向い合う前記一対の基本配線パターン層として、それぞれにおける前記配線パターンの走る方向が、平面的に重ね合わせ状態に見て直交状態に又は斜めに交叉するものを準備し、これらの基本配線パターン層に基づいて配線設計を行うことを特徴とする請求項1又は2に記載の半導体集積回路の配線設計方法。
- 前記基本ビアアレイ層として、前記基本ビアアレイ層における前記ビアは、一方の前記基本配線パターン層における前記配線パターンと他方の前記基本配線パターン層における前記配線パターンとのねじれ状態での直交状態に又は斜めに交叉する交叉点に、それらの配線パターン同士を接続可能に配置されたものを準備し、そのビアアレイ層に基づいて配線設計を行うことを特徴とする請求項3に記載の半導体集積回路の配線設計方法。
- 階層構造をなす少なくとも第1及び第2の2つの配線パターン層とこれらの間に位置するビアアレイ層とを有し、
前記第1及び第2の配線パターン層は、ストリップ状の複数の第1及び第2の配線パターンを有し、前記第1及び第2の配線パターン層における前記第1及び第2の配線パターンはある一定の方向に走っており、前記第1の配線パターンと前記第2の配線パターンとは、ねじれ状態で交叉しており、それらの交叉点の選択的なものに、前記ビアアレイ層の前記ビアが、前記第1及び第2の配線パターンを接続するものとして配置されており、前記第1及び第2の配線パターン層においては配線領域に前記第1及び第2の配線パターンが所定の間隔で繰り返し状態に形成されると共に、前記第1及び第2の配線パターンのあるものは途中で切断されて複数の配線パターン片とされ、前記第1及び第2の配線パターン並びに前記配線パターン片のあるものは前記ビアによって第1及び第2の配線パターン層のもの同士が接続されて信号の通る信号用配線とされ、これ以外のものはダミー用配線とされ、さらに、前記ビアアレイ層においては複数のビアのあるものが前記第1及び第2の配線パターンを接続し、これ以外のビアはダミー用ビアとして形成されている、ことを特徴とする、半導体集積回路。
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JP2003367374A JP4346410B2 (ja) | 2003-10-28 | 2003-10-28 | 半導体集積回路の配線設計方法及び半導体集積回路 |
US10/972,463 US7200831B2 (en) | 2003-10-28 | 2004-10-26 | Semiconductor integrated circuit wiring design method and semiconductor integrated circuit |
KR1020040086166A KR100583709B1 (ko) | 2003-10-28 | 2004-10-27 | 반도체 집적 회로의 배선 설계 방법 및 반도체 집적 회로 |
CNB2004100880120A CN1329984C (zh) | 2003-10-28 | 2004-10-28 | 半导体集成电路的布线设计方法以及半导体集成电路 |
US11/670,568 US7525132B2 (en) | 2003-10-28 | 2007-02-02 | Semiconductor integrated circuit wiring design method and semiconductor integrated circuit |
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Also Published As
Publication number | Publication date |
---|---|
US7525132B2 (en) | 2009-04-28 |
US7200831B2 (en) | 2007-04-03 |
JP4346410B2 (ja) | 2009-10-21 |
US20070120260A1 (en) | 2007-05-31 |
US20050110130A1 (en) | 2005-05-26 |
KR20050040758A (ko) | 2005-05-03 |
KR100583709B1 (ko) | 2006-05-26 |
CN1612323A (zh) | 2005-05-04 |
CN1329984C (zh) | 2007-08-01 |
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