JP2004533726A5 - - Google Patents

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Publication number
JP2004533726A5
JP2004533726A5 JP2003509512A JP2003509512A JP2004533726A5 JP 2004533726 A5 JP2004533726 A5 JP 2004533726A5 JP 2003509512 A JP2003509512 A JP 2003509512A JP 2003509512 A JP2003509512 A JP 2003509512A JP 2004533726 A5 JP2004533726 A5 JP 2004533726A5
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JP
Japan
Prior art keywords
layer
silicon
less
semiconductor material
void
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JP2003509512A
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English (en)
Japanese (ja)
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JP2004533726A (ja
JP4331593B2 (ja
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Priority claimed from DE10131249A external-priority patent/DE10131249A1/de
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Publication of JP2004533726A5 publication Critical patent/JP2004533726A5/ja
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Publication of JP4331593B2 publication Critical patent/JP4331593B2/ja
Anticipated expiration legal-status Critical
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JP2003509512A 2001-06-28 2002-06-27 半導体材料からなるフィルムまたは層およびフィルムまたは層の製造方法 Expired - Lifetime JP4331593B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10131249A DE10131249A1 (de) 2001-06-28 2001-06-28 Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
PCT/EP2002/007125 WO2003003430A2 (de) 2001-06-28 2002-06-27 Film oder schicht aus halbleitendem material und verfahren zur herstellung des films oder der schicht

Publications (3)

Publication Number Publication Date
JP2004533726A JP2004533726A (ja) 2004-11-04
JP2004533726A5 true JP2004533726A5 (enExample) 2005-09-02
JP4331593B2 JP4331593B2 (ja) 2009-09-16

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ID=7689811

Family Applications (1)

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JP2003509512A Expired - Lifetime JP4331593B2 (ja) 2001-06-28 2002-06-27 半導体材料からなるフィルムまたは層およびフィルムまたは層の製造方法

Country Status (9)

Country Link
US (2) US7052948B2 (enExample)
EP (2) EP1626440B1 (enExample)
JP (1) JP4331593B2 (enExample)
KR (1) KR100587997B1 (enExample)
CN (1) CN100372060C (enExample)
AT (1) ATE324670T1 (enExample)
DE (3) DE10131249A1 (enExample)
TW (1) TW575910B (enExample)
WO (1) WO2003003430A2 (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4277481B2 (ja) * 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
JP2004039735A (ja) * 2002-07-01 2004-02-05 Fujitsu Ltd 半導体基板及びその製造方法
EP2280412A3 (en) * 2002-11-29 2011-02-16 STMicroelectronics S.r.l. Semiconductor substrate comprising at least a buried insulating cavity
TW582099B (en) * 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
DE10326578B4 (de) 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
DE10336271B4 (de) * 2003-08-07 2008-02-07 Siltronic Ag Siliciumscheibe und Verfahren zu deren Herstellung
KR100605497B1 (ko) * 2003-11-27 2006-07-28 삼성전자주식회사 에스오아이 기판들을 제조하는 방법들, 이를 사용하여반도체 소자들을 제조하는 방법들 및 그에 의해 제조된반도체 소자들
DE602004027597D1 (de) 2004-03-19 2010-07-22 St Microelectronics Srl Halbleiterdrucksensor und Verfahren zur Herstellung
JP4626175B2 (ja) * 2004-04-09 2011-02-02 株式会社Sumco Soi基板の製造方法
DE102004021113B4 (de) * 2004-04-29 2006-04-20 Siltronic Ag SOI-Scheibe und Verfahren zu ihrer Herstellung
DE102004030612B3 (de) * 2004-06-24 2006-04-20 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
KR100555569B1 (ko) 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
US20100117152A1 (en) * 2007-06-28 2010-05-13 Chang-Woo Oh Semiconductor devices
KR100843717B1 (ko) * 2007-06-28 2008-07-04 삼성전자주식회사 플로팅 바디 소자 및 벌크 바디 소자를 갖는 반도체소자 및그 제조방법
DE102004041378B4 (de) * 2004-08-26 2010-07-08 Siltronic Ag Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung
DE602004010117D1 (de) * 2004-09-16 2007-12-27 St Microelectronics Srl Verfahren zur Hestellung von zusammengestzten Halbleiterplättchen mittels Schichtübertragung
DE102004054564B4 (de) * 2004-11-11 2008-11-27 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
DE102004062356A1 (de) * 2004-12-23 2006-07-13 Siltronic Ag Halbleiterscheibe mit einer Halbleiterschicht und einer darunter liegenden elektrisch isolierenden Schicht sowie Verfahren zu deren Herstellung
DE102005000826A1 (de) 2005-01-05 2006-07-20 Siltronic Ag Halbleiterscheibe mit Silicium-Germanium-Schicht und Verfahren zu deren Herstellung
FR2884647B1 (fr) * 2005-04-15 2008-02-22 Soitec Silicon On Insulator Traitement de plaques de semi-conducteurs
EP1719993A1 (en) * 2005-05-06 2006-11-08 STMicroelectronics S.r.l. Integrated differential pressure sensor and manufacturing process thereof
CN1312328C (zh) * 2005-05-16 2007-04-25 浙江大学 用于纳米光子技术的单晶硅纳米膜的制备方法
US7629209B2 (en) * 2005-10-17 2009-12-08 Chunghwa Picture Tubes, Ltd. Methods for fabricating polysilicon film and thin film transistors
JP4342503B2 (ja) * 2005-10-20 2009-10-14 富士通マイクロエレクトロニクス株式会社 半導体装置および半導体装置の検査方法
KR101171189B1 (ko) * 2005-10-21 2012-08-06 삼성전자주식회사 더미 글래스 기판과 표시장치의 제조방법
FR2895563B1 (fr) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
US7799640B2 (en) * 2006-09-28 2010-09-21 Semiconductor Components Industries, Llc Method of forming a semiconductor device having trench charge compensation regions
KR100882932B1 (ko) * 2007-06-11 2009-02-10 삼성전자주식회사 반도체 기판 및 그 제조 방법, 반도체 소자의 제조 방법 및이미지 센서의 제조 방법
US20090280588A1 (en) * 2008-05-06 2009-11-12 Leo Mathew Method of forming an electronic device including removing a differential etch layer
EP2161741B1 (en) * 2008-09-03 2014-06-11 Soitec Method for fabricating a semiconductor on insulator substrate with reduced SECCO defect density
US20100187572A1 (en) * 2009-01-26 2010-07-29 Cho Hans S Suspended mono-crystalline structure and method of fabrication from a heteroepitaxial layer
DE102009030298B4 (de) 2009-06-24 2012-07-12 Siltronic Ag Verfahren zur lokalen Politur einer Halbleiterscheibe
JP5585056B2 (ja) * 2009-11-19 2014-09-10 富士電機株式会社 Son半導体基板の製造方法
JP5891597B2 (ja) * 2011-04-07 2016-03-23 富士電機株式会社 半導体基板または半導体装置の製造方法
CN102294655A (zh) * 2011-08-10 2011-12-28 开化美盛电子科技有限公司 一种粘固硅棒的载体的制作方法
US9406551B2 (en) 2012-09-27 2016-08-02 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate, and method for manufacturing semiconductor devices integrated in a semiconductor substrate
DE102015209889B4 (de) 2015-05-29 2018-12-06 Siltronic Ag Strukturierte Halbleiterscheibe und Verfahren zu deren Herstellung
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
EP3446111B1 (en) * 2016-08-03 2022-03-09 Hewlett-Packard Development Company, L.P. Conductive wire disposed in a layer
DE102019106124A1 (de) 2018-03-22 2019-09-26 Infineon Technologies Ag Bilden von Halbleitervorrichtungen in Siliciumcarbid
US10943813B2 (en) 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
FR3091000B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Procede de fabrication d’un substrat pour un capteur d’image de type face avant
US11710656B2 (en) * 2019-09-30 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor-on-insulator (SOI) substrate
FR3108774B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
CN113471289B (zh) * 2021-05-19 2024-07-16 广东省大湾区集成电路与系统应用研究院 一种绝缘体上硅衬底及其制备方法、应用

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2901031B2 (ja) * 1992-01-30 1999-06-02 キヤノン株式会社 半導体基材及びその作製方法
EP1251556B1 (en) * 1992-01-30 2010-03-24 Canon Kabushiki Kaisha Process for producing semiconductor substrate
US5427055A (en) 1992-01-31 1995-06-27 Canon Kabushiki Kaisha Method for controlling roughness on surface of monocrystal
FR2715503B1 (fr) * 1994-01-26 1996-04-05 Commissariat Energie Atomique Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation.
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
DE19637182A1 (de) 1996-09-12 1998-03-19 Wacker Siltronic Halbleitermat Verfahren zur Herstellung von Halbleiterscheiben aus Silicium mit geringer Defektdichte
SG65697A1 (en) * 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US6159825A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Controlled cleavage thin film separation process using a reusable substrate
EP0895282A3 (en) * 1997-07-30 2000-01-26 Canon Kabushiki Kaisha Method of preparing a SOI substrate by using a bonding process, and SOI substrate produced by the same
JP3324469B2 (ja) * 1997-09-26 2002-09-17 信越半導体株式会社 Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
JP3472171B2 (ja) * 1997-12-26 2003-12-02 キヤノン株式会社 半導体基材のエッチング方法及びエッチング装置並びにそれを用いた半導体基材の作製方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP3618254B2 (ja) * 1998-06-02 2005-02-09 信越半導体株式会社 Soi基板の製造方法
JP3762144B2 (ja) * 1998-06-18 2006-04-05 キヤノン株式会社 Soi基板の作製方法
TW465101B (en) * 1998-09-04 2001-11-21 Canon Kk Semiconductor substrate and method for producing the same
EP0996145A3 (en) * 1998-09-04 2000-11-08 Canon Kabushiki Kaisha Process for producing semiconductor substrate
JP2000188269A (ja) * 1998-10-16 2000-07-04 Canon Inc 部材の分離方法及び分離装置並びに基板の製造方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
JP3453544B2 (ja) * 1999-03-26 2003-10-06 キヤノン株式会社 半導体部材の作製方法
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
JP4074051B2 (ja) * 1999-08-31 2008-04-09 株式会社東芝 半導体基板およびその製造方法
JP3994602B2 (ja) * 1999-11-12 2007-10-24 信越半導体株式会社 シリコン単結晶ウエーハおよびその製造方法並びにsoiウエーハ
US6660606B2 (en) * 2000-09-29 2003-12-09 Canon Kabushiki Kaisha Semiconductor-on-insulator annealing method
US6489217B1 (en) * 2001-07-03 2002-12-03 Maxim Integrated Products, Inc. Method of forming an integrated circuit on a low loss substrate

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