JP2005526399A5 - - Google Patents

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Publication number
JP2005526399A5
JP2005526399A5 JP2004506080A JP2004506080A JP2005526399A5 JP 2005526399 A5 JP2005526399 A5 JP 2005526399A5 JP 2004506080 A JP2004506080 A JP 2004506080A JP 2004506080 A JP2004506080 A JP 2004506080A JP 2005526399 A5 JP2005526399 A5 JP 2005526399A5
Authority
JP
Japan
Prior art keywords
substrate
sacrificial layer
gate insulating
layer
fluorine atoms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004506080A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005526399A (ja
Filing date
Publication date
Priority claimed from US10/145,519 external-priority patent/US6541321B1/en
Application filed filed Critical
Publication of JP2005526399A publication Critical patent/JP2005526399A/ja
Publication of JP2005526399A5 publication Critical patent/JP2005526399A5/ja
Pending legal-status Critical Current

Links

JP2004506080A 2002-05-14 2002-12-17 厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法 Pending JP2005526399A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/145,519 US6541321B1 (en) 2002-05-14 2002-05-14 Method of making transistors with gate insulation layers of differing thickness
PCT/US2002/040500 WO2003098685A1 (en) 2002-05-14 2002-12-17 Method of making transistors with gate insulation layers of differing thickness

Publications (2)

Publication Number Publication Date
JP2005526399A JP2005526399A (ja) 2005-09-02
JP2005526399A5 true JP2005526399A5 (enExample) 2006-02-16

Family

ID=22513473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004506080A Pending JP2005526399A (ja) 2002-05-14 2002-12-17 厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法

Country Status (7)

Country Link
US (1) US6541321B1 (enExample)
EP (1) EP1504470A1 (enExample)
JP (1) JP2005526399A (enExample)
KR (1) KR100940352B1 (enExample)
CN (1) CN1310314C (enExample)
AU (1) AU2002353166A1 (enExample)
WO (1) WO2003098685A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004519090A (ja) * 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション 歪み表面チャネル及び歪み埋め込みチャネルｍｏｓｆｅｔ素子のゲート技術
WO2002103760A2 (en) * 2001-06-14 2002-12-27 Amberware Systems Corporation Method of selective removal of sige alloys
KR20040077900A (ko) * 2002-02-01 2004-09-07 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 고품질 산화물층 형성 방법 및 비휘발성 메모리 소자
US6879007B2 (en) * 2002-08-08 2005-04-12 Sharp Kabushiki Kaisha Low volt/high volt transistor
CN100521071C (zh) * 2003-07-11 2009-07-29 Nxp股份有限公司 一种半导体器件的制造方法及在这种方法中使用的装置
DE602004024071D1 (de) * 2003-07-11 2009-12-24 Nxp Bv Verfahren für das herstellen eines halbleiterbauelements
US20050112824A1 (en) * 2003-11-26 2005-05-26 Yu-Chang Jong Method of forming gate oxide layers with multiple thicknesses on substrate
JP4040602B2 (ja) * 2004-05-14 2008-01-30 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2006344634A (ja) * 2005-06-07 2006-12-21 Renesas Technology Corp Ｃｍｏｓ型半導体装置の製造方法および、ｃｍｏｓ型半導体装置
US7410874B2 (en) * 2006-07-05 2008-08-12 Chartered Semiconductor Manufacturing, Ltd. Method of integrating triple gate oxide thickness
KR100853796B1 (ko) * 2007-06-07 2008-08-25 주식회사 동부하이텍 반도체 소자의 제조 방법
US20090065820A1 (en) * 2007-09-06 2009-03-12 Lu-Yang Kao Method and structure for simultaneously fabricating selective film and spacer
US8232605B2 (en) * 2008-12-17 2012-07-31 United Microelectronics Corp. Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
US8828834B2 (en) 2012-06-12 2014-09-09 Globalfoundries Inc. Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
US8975143B2 (en) 2013-04-29 2015-03-10 Freescale Semiconductor, Inc. Selective gate oxide properties adjustment using fluorine
US9263270B2 (en) 2013-06-06 2016-02-16 Globalfoundries Inc. Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0136935B1 (ko) * 1994-04-21 1998-04-24 문정환 메모리 소자의 제조방법
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
JP3194370B2 (ja) * 1998-05-11 2001-07-30 日本電気株式会社 半導体装置とその製造方法
JP2000003965A (ja) * 1998-06-15 2000-01-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6335262B1 (en) * 1999-01-14 2002-01-01 International Business Machines Corporation Method for fabricating different gate oxide thicknesses within the same chip
US6251747B1 (en) * 1999-11-02 2001-06-26 Philips Semiconductors, Inc. Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

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