JP2005514765A5 - - Google Patents

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Publication number
JP2005514765A5
JP2005514765A5 JP2003555572A JP2003555572A JP2005514765A5 JP 2005514765 A5 JP2005514765 A5 JP 2005514765A5 JP 2003555572 A JP2003555572 A JP 2003555572A JP 2003555572 A JP2003555572 A JP 2003555572A JP 2005514765 A5 JP2005514765 A5 JP 2005514765A5
Authority
JP
Japan
Prior art keywords
forming
layer
substrate
etching
nitride layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003555572A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005514765A (ja
Filing date
Publication date
Priority claimed from US10/023,328 external-priority patent/US6780776B1/en
Application filed filed Critical
Publication of JP2005514765A publication Critical patent/JP2005514765A/ja
Publication of JP2005514765A5 publication Critical patent/JP2005514765A5/ja
Pending legal-status Critical Current

Links

JP2003555572A 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ Pending JP2005514765A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/023,328 US6780776B1 (en) 2001-12-20 2001-12-20 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
PCT/US2002/041105 WO2003054948A1 (en) 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Publications (2)

Publication Number Publication Date
JP2005514765A JP2005514765A (ja) 2005-05-19
JP2005514765A5 true JP2005514765A5 (enExample) 2006-02-09

Family

ID=21814449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003555572A Pending JP2005514765A (ja) 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ

Country Status (7)

Country Link
US (1) US6780776B1 (enExample)
EP (1) EP1456874A1 (enExample)
JP (1) JP2005514765A (enExample)
KR (1) KR100945915B1 (enExample)
CN (1) CN100367470C (enExample)
AU (1) AU2002358271A1 (enExample)
WO (1) WO2003054948A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721200B1 (ko) * 2005-12-22 2007-05-23 주식회사 하이닉스반도체 반도체소자의 듀얼 게이트 형성방법
WO2007093741A2 (fr) * 2006-02-14 2007-08-23 Stmicroelectronics Crolles 2 Sas Transistor mos a seuil reglable
US7544561B2 (en) * 2006-11-06 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation
KR100874957B1 (ko) * 2007-02-26 2008-12-19 삼성전자주식회사 오프셋 스페이서를 갖는 반도체 소자의 제조방법 및 관련된소자
JP2008098640A (ja) * 2007-10-09 2008-04-24 Toshiba Corp 半導体装置の製造方法
US8854403B2 (en) * 2009-02-06 2014-10-07 Xerox Corporation Image forming apparatus with a TFT backplane for xerography without a light source
US8552507B2 (en) 2009-12-24 2013-10-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN108206160B (zh) * 2016-12-20 2020-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2219434A (en) 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
JPH0817235B2 (ja) * 1990-08-29 1996-02-21 株式会社東芝 オフセットゲート構造トランジスタおよびその製造方法
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
JP3238551B2 (ja) * 1993-11-19 2001-12-17 沖電気工業株式会社 電界効果型トランジスタの製造方法
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5670404A (en) 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5899719A (en) * 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5912188A (en) 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6165831A (en) 1998-11-20 2000-12-26 United Microelectronics Corp. Method of fabricating a buried contact in a static random access memory
US6187645B1 (en) 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6294432B1 (en) 1999-12-20 2001-09-25 United Microelectronics Corp. Super halo implant combined with offset spacer process
TW463251B (en) * 2000-12-08 2001-11-11 Macronix Int Co Ltd Manufacturing method of gate structure

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