JP4817677B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- JP4817677B2 JP4817677B2 JP2005061167A JP2005061167A JP4817677B2 JP 4817677 B2 JP4817677 B2 JP 4817677B2 JP 2005061167 A JP2005061167 A JP 2005061167A JP 2005061167 A JP2005061167 A JP 2005061167A JP 4817677 B2 JP4817677 B2 JP 4817677B2
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
Description
図1及び図2はこの実施形態の半導体素子の製造方法を説明するための概略工程図で、断面の切り口で示してある。
図3は半導体素子の製造方法の参考例を説明するための概略工程図で、断面の切り口で示してある。
11 下地基板
12 支持基板
14 絶縁層
16 SOI層
17 活性SOI層
18 素子分離絶縁層
20、22 パッド酸化膜
30、32 シリコン窒化膜
40、70 フォトレジストマスク
42 活性領域
44 素子分離領域
50 高誘電体非結晶膜
52、54、57 ゲート絶縁膜
55 高誘電体結晶膜
56 高誘電体膜
58 ダメージ層(高誘電体非結晶膜)
60 アモルファスシリコン膜
62 ゲート電極形成用膜
64、67 ゲート電極
65 ポリシリコン膜
72 ゲート形成領域
74 ゲート非形成領域
Claims (7)
- 下地基板を用意する工程と、
該下地基板上に、高誘電率材の高誘電体非結晶膜を形成する工程と、
該高誘電体非結晶膜上に、前記高誘電率材の非結晶化温度を成膜温度としてアモルファスシリコン膜を形成する工程と、
フォトリソグラフィ法により、ゲート形成領域の前記アモルファスシリコン膜上にフォトレジストマスクを形成する工程と、
該フォトレジストマスクを用いたドライエッチングにより、ゲート非形成領域の前記アモルファスシリコン膜を除去して前記高誘電体非結晶膜を露出させるとともに、前記ゲート形成領域の前記アモルファスシリコン膜を残存させてゲート電極形成用膜を形成する工
程と、
前記フォトレジストマスクを除去した後、前記ゲート電極形成用膜をマスクとしたウェットエッチングにより、前記ゲート電極形成用膜で覆われた前記高誘電体非結晶膜の部分を残存させ、露出している前記高誘電体非結晶膜の部分を除去する工程と、
前記ゲート電極形成用膜に対して熱処理を行うことにより、アモルファスシリコンをポリシリコンに改質してゲート電極にするととともに、残存する前記高誘電体非結晶膜の部分を結晶化して高誘電体結晶膜にする工程と
を備えることを特徴とする半導体素子の製造方法。 - SOI基板のSOI層に素子分離絶縁層を形成したものを下地基板として用意することを特徴とする請求項1に記載の半導体素子の製造方法。
- 基板上に非結晶の高誘電体膜を形成する工程と、
前記非結晶の高誘電体膜が結晶化する温度よりも低い温度で、前記非結晶の高誘電体膜上にアモルファスシリコン膜を形成する工程と、
前記アモルファスシリコン膜及び前記非結晶の高誘電体膜をパターニングする工程と、
パターニングされた前記アモルファスシリコン膜に対して熱処理を施すことにより、パターニングされた前記アモルファスシリコン膜及び前記非結晶の高誘電体膜を結晶化する工程と
を備えることを特徴とする半導体素子の製造方法。 - 前記アモルファスシリコン膜を結晶化する工程では、パターニングされた前記アモルファスシリコン膜を多結晶シリコン膜に改質する
ことを特徴とする請求項3に記載の半導体素子の製造方法。 - 前記パターニングする工程は、
前記アモルファスシリコン膜をパターニングする工程と、
パターニングされた前記アモルファスシリコン膜をマスクとして前記非結晶の高誘電体膜をパターニングする工程と
を含むことを特徴とする請求項3又は4に記載の半導体素子の製造方法。 - 前記非結晶の高誘電体膜をパターニングする工程は、ウェットエッチングで行われることを特徴とする請求項5に記載の半導体素子の製造方法。
- 前記基板は、絶縁層上に形成されたシリコン層を含み、前記非結晶の高誘電体膜は前記シリコン層上に形成される
ことを特徴とする請求項3〜6のいずれか1項に記載の半導体素子の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2005061167A JP4817677B2 (ja) | 2005-03-04 | 2005-03-04 | 半導体素子の製造方法 |
US11/366,384 US7566617B2 (en) | 2005-03-04 | 2006-03-03 | Method for manufacturing semiconductor elemental device forming an amorphous high dielectric film and an amorphous silicon film |
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JP2005061167A JP4817677B2 (ja) | 2005-03-04 | 2005-03-04 | 半導体素子の製造方法 |
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JP2006245433A JP2006245433A (ja) | 2006-09-14 |
JP4817677B2 true JP4817677B2 (ja) | 2011-11-16 |
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JP2005061167A Expired - Fee Related JP4817677B2 (ja) | 2005-03-04 | 2005-03-04 | 半導体素子の製造方法 |
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US (1) | US7566617B2 (ja) |
JP (1) | JP4817677B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006278550A (ja) * | 2005-03-28 | 2006-10-12 | Fujitsu Ltd | 半導体装置の製造方法 |
US7635634B2 (en) * | 2007-04-16 | 2009-12-22 | Infineon Technologies Ag | Dielectric apparatus and associated methods |
JP5601363B2 (ja) * | 2012-11-19 | 2014-10-08 | ソニー株式会社 | 半導体装置、薄膜トランジスタ基板および表示装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3169654B2 (ja) * | 1991-11-27 | 2001-05-28 | 松下電子工業株式会社 | 半導体装置の製造方法 |
JP2002184973A (ja) * | 2000-12-11 | 2002-06-28 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP4034627B2 (ja) * | 2001-09-28 | 2008-01-16 | テキサス インスツルメンツ インコーポレイテツド | 集積回路及びその製造方法 |
US6667246B2 (en) * | 2001-12-04 | 2003-12-23 | Matsushita Electric Industrial Co., Ltd. | Wet-etching method and method for manufacturing semiconductor device |
JP3727299B2 (ja) * | 2001-12-04 | 2005-12-14 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP3652324B2 (ja) | 2002-05-16 | 2005-05-25 | 弘塑科技股▲ふん▼有限公司 | 高絶縁性薄層の低温ウェットエッチング法 |
JP4150548B2 (ja) * | 2002-08-08 | 2008-09-17 | 富士通株式会社 | 半導体装置の製造方法 |
US6869868B2 (en) * | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
JP4082280B2 (ja) * | 2003-05-30 | 2008-04-30 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
TWI294648B (en) * | 2003-07-24 | 2008-03-11 | Au Optronics Corp | Method for manufacturing polysilicon film |
US6818516B1 (en) * | 2003-07-29 | 2004-11-16 | Lsi Logic Corporation | Selective high k dielectrics removal |
-
2005
- 2005-03-04 JP JP2005061167A patent/JP4817677B2/ja not_active Expired - Fee Related
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2006
- 2006-03-03 US US11/366,384 patent/US7566617B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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US7566617B2 (en) | 2009-07-28 |
US20060199327A1 (en) | 2006-09-07 |
JP2006245433A (ja) | 2006-09-14 |
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