AU2002358271A1 - Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer - Google Patents

Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Info

Publication number
AU2002358271A1
AU2002358271A1 AU2002358271A AU2002358271A AU2002358271A1 AU 2002358271 A1 AU2002358271 A1 AU 2002358271A1 AU 2002358271 A AU2002358271 A AU 2002358271A AU 2002358271 A AU2002358271 A AU 2002358271A AU 2002358271 A1 AU2002358271 A1 AU 2002358271A1
Authority
AU
Australia
Prior art keywords
layer
etch stop
offset spacer
stop layer
silicon recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002358271A
Other languages
English (en)
Inventor
Darin A. Chan
William G. En
Mark W. Michael
John G. Pellerin
Wen-Jie Qi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2002358271A1 publication Critical patent/AU2002358271A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
AU2002358271A 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer Abandoned AU2002358271A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/023,328 US6780776B1 (en) 2001-12-20 2001-12-20 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
US10/023,328 2001-12-20
PCT/US2002/041105 WO2003054948A1 (en) 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Publications (1)

Publication Number Publication Date
AU2002358271A1 true AU2002358271A1 (en) 2003-07-09

Family

ID=21814449

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002358271A Abandoned AU2002358271A1 (en) 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Country Status (7)

Country Link
US (1) US6780776B1 (enExample)
EP (1) EP1456874A1 (enExample)
JP (1) JP2005514765A (enExample)
KR (1) KR100945915B1 (enExample)
CN (1) CN100367470C (enExample)
AU (1) AU2002358271A1 (enExample)
WO (1) WO2003054948A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721200B1 (ko) * 2005-12-22 2007-05-23 주식회사 하이닉스반도체 반도체소자의 듀얼 게이트 형성방법
JP2009527103A (ja) * 2006-02-14 2009-07-23 エス テ マイクロエレクトロニクス クロル ２ エス アー エス 閾値が調整可能なｍｏｓトランジスタ
US7544561B2 (en) * 2006-11-06 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation
KR100874957B1 (ko) * 2007-02-26 2008-12-19 삼성전자주식회사 오프셋 스페이서를 갖는 반도체 소자의 제조방법 및 관련된소자
JP2008098640A (ja) * 2007-10-09 2008-04-24 Toshiba Corp 半導体装置の製造方法
US8854403B2 (en) * 2009-02-06 2014-10-07 Xerox Corporation Image forming apparatus with a TFT backplane for xerography without a light source
CN102640280B (zh) 2009-12-24 2015-03-11 瑞萨电子株式会社 半导体器件及其制造方法
CN108206160B (zh) * 2016-12-20 2020-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2219434A (en) 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
JPH0817235B2 (ja) * 1990-08-29 1996-02-21 株式会社東芝 オフセットゲート構造トランジスタおよびその製造方法
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
JP3238551B2 (ja) * 1993-11-19 2001-12-17 沖電気工業株式会社 電界効果型トランジスタの製造方法
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5670404A (en) 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5899719A (en) * 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5912188A (en) 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6165831A (en) 1998-11-20 2000-12-26 United Microelectronics Corp. Method of fabricating a buried contact in a static random access memory
US6187645B1 (en) 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6294432B1 (en) 1999-12-20 2001-09-25 United Microelectronics Corp. Super halo implant combined with offset spacer process
TW463251B (en) * 2000-12-08 2001-11-11 Macronix Int Co Ltd Manufacturing method of gate structure

Also Published As

Publication number Publication date
EP1456874A1 (en) 2004-09-15
US6780776B1 (en) 2004-08-24
CN100367470C (zh) 2008-02-06
JP2005514765A (ja) 2005-05-19
KR100945915B1 (ko) 2010-03-05
KR20040068964A (ko) 2004-08-02
WO2003054948A1 (en) 2003-07-03
CN1606798A (zh) 2005-04-13

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase