JP2005514765A - エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ - Google Patents

エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ Download PDF

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JP2005514765A
JP2005514765A JP2003555572A JP2003555572A JP2005514765A JP 2005514765 A JP2005514765 A JP 2005514765A JP 2003555572 A JP2003555572 A JP 2003555572A JP 2003555572 A JP2003555572 A JP 2003555572A JP 2005514765 A JP2005514765 A JP 2005514765A
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layer
substrate
forming
polysilicon
nitride
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JP2005514765A5 (enExample
Inventor
キ ウェン−ジー
ジー． ペレリン ジョン
ジー． エン ウィリアム
ダブリュ． マイケル マーク
エイ． チャン ダリン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2003555572A 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ Pending JP2005514765A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/023,328 US6780776B1 (en) 2001-12-20 2001-12-20 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
PCT/US2002/041105 WO2003054948A1 (en) 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Publications (2)

Publication Number Publication Date
JP2005514765A true JP2005514765A (ja) 2005-05-19
JP2005514765A5 JP2005514765A5 (enExample) 2006-02-09

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JP2003555572A Pending JP2005514765A (ja) 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ

Country Status (7)

Country Link
US (1) US6780776B1 (enExample)
EP (1) EP1456874A1 (enExample)
JP (1) JP2005514765A (enExample)
KR (1) KR100945915B1 (enExample)
CN (1) CN100367470C (enExample)
AU (1) AU2002358271A1 (enExample)
WO (1) WO2003054948A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552507B2 (en) 2009-12-24 2013-10-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
KR100721200B1 (ko) * 2005-12-22 2007-05-23 주식회사 하이닉스반도체 반도체소자의 듀얼 게이트 형성방법
WO2007093741A2 (fr) * 2006-02-14 2007-08-23 Stmicroelectronics Crolles 2 Sas Transistor mos a seuil reglable
US7544561B2 (en) * 2006-11-06 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation
KR100874957B1 (ko) * 2007-02-26 2008-12-19 삼성전자주식회사 오프셋 스페이서를 갖는 반도체 소자의 제조방법 및 관련된소자
JP2008098640A (ja) * 2007-10-09 2008-04-24 Toshiba Corp 半導体装置の製造方法
US8854403B2 (en) * 2009-02-06 2014-10-07 Xerox Corporation Image forming apparatus with a TFT backplane for xerography without a light source
CN108206160B (zh) * 2016-12-20 2020-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Citations (3)

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JPH053206A (ja) * 1990-08-29 1993-01-08 Toshiba Corp オフセツトゲート構造トランジスタおよびその製造方法
JPH05102185A (ja) * 1991-04-01 1993-04-23 Sgs Thomson Microelectron Inc 改良型電界効果トランジスタ構成体及び製造方法
JPH07142726A (ja) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法

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GB2219434A (en) 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5670404A (en) 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5899719A (en) * 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5912188A (en) 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6165831A (en) 1998-11-20 2000-12-26 United Microelectronics Corp. Method of fabricating a buried contact in a static random access memory
US6187645B1 (en) 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6294432B1 (en) 1999-12-20 2001-09-25 United Microelectronics Corp. Super halo implant combined with offset spacer process
TW463251B (en) * 2000-12-08 2001-11-11 Macronix Int Co Ltd Manufacturing method of gate structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH053206A (ja) * 1990-08-29 1993-01-08 Toshiba Corp オフセツトゲート構造トランジスタおよびその製造方法
JPH05102185A (ja) * 1991-04-01 1993-04-23 Sgs Thomson Microelectron Inc 改良型電界効果トランジスタ構成体及び製造方法
JPH07142726A (ja) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552507B2 (en) 2009-12-24 2013-10-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
EP1456874A1 (en) 2004-09-15
CN100367470C (zh) 2008-02-06
KR20040068964A (ko) 2004-08-02
KR100945915B1 (ko) 2010-03-05
CN1606798A (zh) 2005-04-13
WO2003054948A1 (en) 2003-07-03
AU2002358271A1 (en) 2003-07-09
US6780776B1 (en) 2004-08-24

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