CN101288180A - 半导体结构的形成方法 - Google Patents
半导体结构的形成方法 Download PDFInfo
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Abstract
一种形成半导体结构的方法包括形成硅的第一层(10)以及然后邻接硅层(10)形成硅锗的第二层(12)。然后邻接第二层(12)形成薄的硅的第三层(14)。接着利用常规的互补金属氧化物半导体(CMOS)工艺在硅的第三层(14)上形成栅极结构。然后在第二层(12)中形成沟槽并且将该结构暴露到热气态化学蚀刻剂,例如加热的盐酸。该蚀刻剂移除硅锗,由此形成Silicon-On-Nothing结构。之后,应用常规的CMOS处理技术完成该结构作为金属氧化物半导体场效应晶体管,包括由氮化硅形成间隔物侧壁(28),氮化硅(30)还填充了通过移除硅锗而形成在硅的第三层(14)下面的空腔。
Description
技术领域
本发明涉及一种形成例如包括设置在两层半导体材料之间的介质材料层这种类型的半导体结构的方法。
背景技术
在半导体器件制备领域,在制造某些半导体器件时进行牺牲层的各向同性横向蚀刻是已知的。例如,所谓的“Silicon-On-Nothing”(SON)金属氧化物半导体场效应晶体管(MOSFET)使用硅-锗(SiGe)牺牲层将薄硅层设置在栅叠层下面,其用作MOSFET有源区,使用薄的硅有源区提供显著的器件性能优点。作为MOSFET的制备工艺的一部分,Si-Ge牺牲层被横向蚀刻并用氧化物缓冲层代替。
为了蚀刻Si-Ge牺牲层,在下游或远程等离子体工具例如化学下游蚀刻器(chemical downstream etcher,CDE)或去耦等离子源(DPS)中,采用湿法化学蚀刻溶液或各向同性等离子蚀刻技术。
尽管使用各向同性等离子蚀刻由于硅和硅-锗之间的电化学电位差而会导致非常高选择性蚀刻,但很难控制并且不容易原位监视。而且,用于横向蚀刻的等离子蚀刻目前没有提供足够的选择性,这是因为当完成硅-锗蚀刻或到达蚀刻终点时会失去选择性。对于一些应用,还可能必须提供抗蚀剂或氧化物硬掩模的另外的掩模层,以使得能够使用等离子蚀刻。
关于湿法化学蚀刻溶液的使用,它们也会遇到许多不利问题。实际上,尽管也是选择性的,使用这样的溶液会导致对正在被蚀刻的器件的极小和精巧的薄特征的机械损伤。另外,很难监测湿法化学蚀刻的进展,因为没有可直接测量的参数可用,例如借助光发射。而且,用于横向蚀刻的湿法化学蚀刻溶液的使用可能受制于纳米尺寸特征中蚀刻溶液的润湿。而且,像DPS一样,湿法化学蚀刻也难以控制并且会遇到在Si-Ge终点选择性损失的问题。
发明内容
根据本发明,提供一种如所附权利要求中所述的形成半导体结构的方法。
附图说明
现在将参考附图仅以示例的方式描述本发明的至少一个实施例,在附图中:
图1是3层半导体材料的基础层的示意图;
图2是补充了用于形成栅叠层的绝缘层和电极层的图1的基础层的示意图;
图3是由图2的结构形成的栅叠层的示意图;
图4是根据本发明实施例的形成在图3的结构中的沟槽的示意图;
图5是根据本发明实施例的从图4的结构移除的牺牲层的示意图;和
图6是根据本发明实施例的部分完成的器件的示意图。
具体实施方式
贯穿以下描述,相同的附图标记用于表示相同的部分。
参考图1,根据已知的互补金属氧化物半导体(CMOS)处理技术,通过首先生长构成第一层半导体材料的硅衬底10形成金属氧化物半导体场效应(MOSFET)晶体管器件5。然后利用已知的合适的外延沉积技术,在硅衬底10上生长30nm厚的第二层(硅-锗)12。之后在硅-锗层12上生长20nm厚的第三层(硅)14。
转向图2,然后利用常规的CMOS处理技术形成栅叠层。在该实例中,然后在硅层14上沉积介质材料,例如二氧化硅(SiO2),或典型地介电常数比硅的介电常数大的材料,也称作高K材料,作为栅绝缘层16。生长足够厚的栅绝缘层16以组成高质量的介质层。典型地,生长厚度在约15和30埃之间的栅绝缘层16,这取决于材料的介电常数和技术应用。
其后,在栅绝缘层16上方沉积多晶硅(PolySi)或金属以形成栅电极层18并用作栅电极。
然后对栅绝缘层16和栅电极层18进行初始蚀刻(图3)以形成栅叠层,栅绝缘层16分享栅电极层18的轮廓。因此,暴露出硅层14的上表面22。
利用常规的CMOS处理技术(图4),典型地利用其是用于形成有源区的掩模的尺寸修正的掩模,使用光致抗蚀剂图案(未示出)保护有源区。
可选地,可以使用其它掩模材料形成该掩模,这取决于制备整合的最佳顺序,例如使用氮化硅(SiN)在栅叠层20上形成硬掩模,因为SiN对氟和氯核素蚀刻剂具有高的抗耐性。
利用光致抗蚀剂图案,将一对沟槽24蚀刻进硅层14的区域中以分别用于源区和漏区。利用标准反应离子蚀刻(RIE)工艺蚀刻该对沟槽24,由此在硅层14中生成了开口以暴露出Si-Ge层12。为了控制蚀刻工艺,光发射谱(OES)信号能提供检测RIE工艺结束的能力,也称作终点检测。一旦沟槽已经穿透了Si-Ge层12,或当沟槽24开始穿透衬底10时,就停止沟槽24的蚀刻。
然后将一般形成为半导体晶片(未示出)一部分的器件5放置在热反应器中,例如,单晶片外延沉积工具或快速热处理(RTP)工具。在该工具内部,将Si-Ge层12暴露到热的气态化学蚀刻剂,例如气态盐酸。通过加热将盐酸保持在气相,气态盐酸保持在约600℃和900℃之间的温度下,例如在约700℃和800℃之间,如在约750℃和800℃之间。另外,工具内的压力低于大气压,典型地为0.1至0.5ATM(100mTorr至500mTorr)并且可以与惰性稀释气体(dialutant gas)一起使用,例如氩或氦。使用稀释剂和减压用于提高环境气体(用稀释气体稀释的气态盐酸)的控制和蚀刻剂气体流动的均匀性,并且对于典型的单晶片处理工具使反应剂流动减小到100至200sccm。
在气相,化学蚀刻剂各向同性蚀刻并且提供在大于100∶1量级的高选择性以有利于硅锗。对于实用目的,可以认为该选择性几乎无穷大。
尽管在该实例中使用了加热的气态盐酸,但本领域技术人员将意识到,根据要蚀刻的材料可以使用其它的热气态蚀刻剂,例如氯(Cl2)氯化硼(BCl3)或其它合适的卤素气体。
参考图5,热的气态化学蚀刻剂各向同性地横向蚀刻Si-Ge层12,直至全部的Si-Ge层12被基本移除,并且在该方面中,可以再次利用OES终点来控制蚀刻剂的处理进程,在硅层14下面,即在硅层14和衬底10之间,留下了空腔26。
一旦已经从栅叠层20下面的一部分硅层14,即将用作器件5的沟道的那部分硅层14下面移除了硅-锗,当使用时,利用标准的原位氧化步骤和/或分离的所谓的“等离子灰化”工艺移除该光致抗蚀剂。
之后,使用另一常规的CMOS处理技术,来沉积邻接栅叠层20两侧的氮化硅(Si3N4)30的侧壁间隔物28。在沉积侧壁间隔物28期间,氮化硅30还经由该对沟槽24进入空腔26,并且用氮化硅间隔物材料30填充空腔26。可选地,可以借助分离的沉积阶段填充该空腔至产生侧壁间隔物28。可以使用分离的沉积阶段来用与氮化硅不同的材料填充栅叠层20下面的空腔26,例如高发射率(高k)的介质,来提高有源区与体衬底或者用以形成产生多栅(“全围绕的栅”)结构的底栅电极的介质和导体(多晶硅)的组合的电隔离。作为另一备选方案,空腔26可以保持为空。
随后(未示于图6),利用常规的CMOS处理技术分别在硅层14中的栅叠层20的任一侧形成源区和漏区。实际上,根据常规的CMOS处理技术完成器件5的其余部分,并且因此为了清楚和简明描述的起见,这里将不再进一步描述。
从上述的实例,本领域技术人员将意识到,可以改变Si-Ge层12的厚度,以改变空腔26的容积。
尽管迄今未描述,但以上描述的晶体管器件可以构成易失性存储单元中的一位,例如随机存取存储器(RAM),如静态的RAM,与许多类似构造的晶体管共用硅有源层12。事实上,本领域技术人员应明白,移除牺牲Si-Ge层12的蚀刻工艺不限制于MOSFET或者甚至晶体管的形成,而是可以用于其中需要各向同性横向选择性蚀刻的其它应用的一般工艺,例如在利用体衬底形成Silicon-On-Nothing(SON)结构或其它三维器件结构中。实际上,上述的热气态化学蚀刻工艺可应用到例如纳米尺寸器件的制造,例如包括非常薄的悬置的硅结构的微机电系统器件。
由此能够提供一种形成半导体结构的方法,其提供比用于制备silicon on nothing器件的现有蚀刻技术大的蚀刻选择率。另外,生成该结构需要的工具本质上比用于移除牺牲层例如硅锗层12的现有工具更简单。而且,工艺参数,例如时间、温度、气体流速和压力,相比用于移除牺牲层的现有工具使用的参数更可控制。因此,减小了工艺复杂性,导致制造成本显著节省。
权利要求书(按照条约第19条的修改)
根据PCT第19(1)条的声明
飞思卡尔半导体公司的专利申请PCT/EP2005/008199修改及其依据:
(i)修正权利要求1来陈述各向同性蚀刻的特征;权利要求1在其倒数第二段处更正了。修改依据见说明书第11页第10行;以及
(ii)随后的权利要求2至21未改变。
1.一种形成半导体结构(5)的方法,该方法包括以下步骤:
设置第一半导体材料层(10);
邻接所述第一半导体材料层(10)设置第二半导体材料层(12);
邻接所述第二半导体材料层(12)设置第三半导体材料层(14);
暴露所述第二半导体材料层(12)以便蚀刻剂通向它;
其特征在于如下步骤:
将所述第二半导体材料层(12)暴露于热气态化学蚀刻剂,该热气态蚀刻剂横向且各向同性地蚀刻所述第二半导体材料层(12),以在所述第一和第三半导体材料层(10,14)之间形成空腔(26);其中:
所述第二半导体材料层(12)由与所述第一和第三半导体材料层(10,14)不同的材料形成。
2.如权利要求1所述的方法,其中该热气态蚀刻剂选择性地有利于蚀刻所述第二半导体材料层(12)。
Claims (21)
1.一种形成半导体结构(5)的方法,该方法包括以下步骤:
设置第一半导体材料层(10);
邻接所述第一半导体材料层(10)设置第二半导体材料层(12);
邻接所述第二半导体材料层(12)设置第三半导体材料层(14);
暴露所述第二半导体材料层(12)以便蚀刻剂通向它;
其特征在于如下步骤:
将所述第二半导体材料层(12)暴露于热气态化学蚀刻剂,该热气态蚀刻剂横向蚀刻所述第二半导体材料层(12),以在所述第一和第三半导体材料层(10,14)之间形成空腔(26);其中:
所述第二半导体材料层(12)由与所述第一和第二半导体材料层(10,14)不同的材料形成。
2.如权利要求1所述的方法,其中该热气态蚀刻剂选择性地有利于蚀刻所述第二半导体材料层(12)。
3.如权利要求1或权利要求2所述的方法,其中该热气态蚀刻剂处在约700℃和800℃之间的温度。
4.如在前权利要求中任一项所述的方法,其中该热气态蚀刻剂处在约600℃和900℃之间的温度。
5.如在前权利要求中任一项所述的方法,其中在预定压力下将该热气态蚀刻剂暴露到所述第二半导体材料层(12)。
6.如权利要求5所述的方法,其中所述预定压力在约10mTorr和约500mTorr之间。
7.如权利要求6所述的方法,其中所述预定压力在约50mTorr和约100mTorr之间。
8.如在前权利要求中任一项所述的方法,其中所述第一半导体材料层(10)由与所述第三半导体材料层(14)不同的材料形成。
9.如权利要求1至7中任一项所述的方法,其中所述第一半导体材料层(10)是硅层。
10.如权利要求1至7中任一项所述的方法,其中所述第三半导体材料层是硅。
11.如在前权利要求中任一项所述的方法,其中所述第二半导体材料层(12)是牺牲层。
12.如在前权利要求中任一项所述的方法,其中所述第二半导体材料层(12)是硅-锗层。
13.如在前权利要求中任一项所述的方法,其中该热气态化学蚀刻剂是气态盐酸。
14.如在前权利要求中任一项所述的方法,其中该半导体结构(5)是晶体管。
15.如权利要求14所述的方法,其中该晶体管是场效应晶体管(FET)。
16.如权利要求14或权利要求15所述的方法,其中该晶体管是互补金属氧化物半导体(CMOS)晶体管。
17.如在前权利要求中任一项所述的方法,其中所述第一半导体材料层(10)是衬底。
18.如在前权利要求中任一项所述的方法,其中设置所述第三半导体材料层(14)的所述步骤组成沟道的形成。
19.如在前权利要求中任一项所述的方法,进一步包括以下步骤:
用介质材料(30)填充该空腔(26)。
20.如在前权利要求中任一项所述的方法,该热气态化学蚀刻剂混合有稀释气体。
21.如权利要求20所述的方法,该稀释气体是惰性气体。
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