TW200707594A - Method of forming a semiconductor structure - Google Patents

Method of forming a semiconductor structure

Info

Publication number
TW200707594A
TW200707594A TW095121983A TW95121983A TW200707594A TW 200707594 A TW200707594 A TW 200707594A TW 095121983 A TW095121983 A TW 095121983A TW 95121983 A TW95121983 A TW 95121983A TW 200707594 A TW200707594 A TW 200707594A
Authority
TW
Taiwan
Prior art keywords
silicon
layer
forming
metal oxide
oxide semiconductor
Prior art date
Application number
TW095121983A
Other languages
Chinese (zh)
Other versions
TWI424504B (en
Inventor
Terry Sparks
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200707594A publication Critical patent/TW200707594A/en
Application granted granted Critical
Publication of TWI424504B publication Critical patent/TWI424504B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor structure comprises forming a first layer of silicon (10) and then forming a second, silicon germanium, layer (12) adjacent the silicon layer (10). A thin third layer of silicon (14) is then formed adjacent the second layer (12). A gate structure is then formed upon the third layer of silicon (14) using convention Complementary Metal Oxide Semiconductor (CMOS) processes. Trenches are then formed into the second layer (12) and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls (28) from silicon nitride, the silicon nitride (30) also filling a cavity formed beneath the third layer of silicon (14) by removal of the silicon germanium.
TW095121983A 2005-06-30 2006-06-20 Method of forming a semiconductor structure TWI424504B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2005/008199 WO2007003220A1 (en) 2005-06-30 2005-06-30 Method of forming a semiconductor structure

Publications (2)

Publication Number Publication Date
TW200707594A true TW200707594A (en) 2007-02-16
TWI424504B TWI424504B (en) 2014-01-21

Family

ID=35385011

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095121983A TWI424504B (en) 2005-06-30 2006-06-20 Method of forming a semiconductor structure

Country Status (6)

Country Link
US (2) US8105890B2 (en)
EP (1) EP1911098A1 (en)
JP (1) JP2008547238A (en)
CN (1) CN101288180A (en)
TW (1) TWI424504B (en)
WO (1) WO2007003220A1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7776745B2 (en) * 2006-02-10 2010-08-17 Stmicroelectronics S.A. Method for etching silicon-germanium in the presence of silicon
CN102842616B (en) * 2011-06-20 2015-06-24 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN102856376B (en) * 2011-06-30 2016-08-03 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN103035709B (en) * 2011-09-30 2015-11-25 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN103258742B (en) * 2012-02-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 The formation method of transistor
CN103377925A (en) * 2012-04-13 2013-10-30 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN103426764B (en) * 2012-05-24 2015-12-09 中芯国际集成电路制造(上海)有限公司 The formation method of transistor
US8907483B2 (en) 2012-10-10 2014-12-09 Globalfoundries Inc. Semiconductor device having a self-forming barrier layer at via bottom
CN104425277B (en) * 2013-09-04 2017-12-29 中芯国际集成电路制造(上海)有限公司 The forming method of transistor
JP6426489B2 (en) * 2015-02-03 2018-11-21 東京エレクトロン株式会社 Etching method
CN109075075B (en) * 2016-04-05 2023-06-06 Tes股份有限公司 Selective etching method for silicon oxide film
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures
DE102017125217A1 (en) * 2017-10-27 2019-05-02 Osram Opto Semiconductors Gmbh Method for producing at least one optoelectronic component and optoelectronic component
JP7345334B2 (en) * 2019-09-18 2023-09-15 東京エレクトロン株式会社 Etching method and substrate processing system

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
FR2795555B1 (en) * 1999-06-28 2002-12-13 France Telecom METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING AN ALTERNATIVELY STACKED LAYER OF SILICON AND LAYERS OF DIELECTRIC MATERIAL
DE19941042A1 (en) 1999-08-28 2001-03-15 Bosch Gmbh Robert Process for the production of surface micromechanical structures by etching with a vaporous, hydrofluoric acid-containing etching medium
FR2799307B1 (en) 1999-10-01 2002-02-15 France Telecom SEMICONDUCTOR DEVICE COMBINING THE ADVANTAGES OF MASSIVE ARCHITECTURES AND ITSELF, MANUFACTURING METHOD
FR2806833B1 (en) * 2000-03-27 2002-06-14 St Microelectronics Sa METHOD FOR MANUFACTURING A MOS TRANSISTOR WITH TWO GRIDS, ONE OF WHICH IS BURIED, AND TRANSISTOR THEREFOR
US6306698B1 (en) * 2000-04-25 2001-10-23 Advanced Micro Devices, Inc. Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same
WO2002059939A2 (en) 2000-11-22 2002-08-01 The Johns Hopkins University Method for fabricating a semiconductor device
DE10142952A1 (en) 2001-06-13 2002-12-19 Bosch Gmbh Robert Production of micromechanical structure used as sensor or actuator comprises preparing micromechanical structure with micromechnical structural elements, and selectively etching
FR2858876B1 (en) * 2003-08-12 2006-03-03 St Microelectronics Sa METHOD FOR FORMATION UNDER A THIN LAYER OF A FIRST MATERIAL OF PORTIONS OF ANOTHER MATERIAL AND / OR VACUUM ZONES
JP4004448B2 (en) * 2003-09-24 2007-11-07 富士通株式会社 Semiconductor device and manufacturing method thereof
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7923782B2 (en) * 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
CN101030602B (en) * 2007-04-06 2012-03-21 上海集成电路研发中心有限公司 MOS transistor for decreasing short channel and its production
US7928474B2 (en) * 2007-08-15 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd., Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
KR101083644B1 (en) * 2008-07-04 2011-11-16 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8299453B2 (en) * 2009-03-03 2012-10-30 International Business Machines Corporation CMOS transistors with silicon germanium channel and dual embedded stressors
US8138523B2 (en) * 2009-10-08 2012-03-20 International Business Machines Corporation Semiconductor device having silicon on stressed liner (SOL)
US8237197B2 (en) * 2010-07-07 2012-08-07 International Business Machines Corporation Asymmetric channel MOSFET

Also Published As

Publication number Publication date
US20080207004A1 (en) 2008-08-28
TWI424504B (en) 2014-01-21
US8105890B2 (en) 2012-01-31
EP1911098A1 (en) 2008-04-16
WO2007003220A1 (en) 2007-01-11
US8587070B2 (en) 2013-11-19
US20120126289A1 (en) 2012-05-24
CN101288180A (en) 2008-10-15
JP2008547238A (en) 2008-12-25

Similar Documents

Publication Publication Date Title
TW200707594A (en) Method of forming a semiconductor structure
US9673222B2 (en) Fin isolation structures facilitating different fin isolation schemes
CN102194756B (en) Fin field effect transistor and method of making the same
CN101986423B (en) Method for forming high germanium concentration sige stressor and integrated circuit transistor structure
JP2012504327A5 (en)
CN105023840B (en) Strain semiconductor device with recess channel and the method for forming the device
TW200636873A (en) Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
JP2012504345A5 (en)
SG137760A1 (en) Method of fabricating a transistor structure
JP2003273240A5 (en)
JP2008010871A (en) Mosfets comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same
TW200509183A (en) Semiconductor device and process for fabricating the same
TW200620456A (en) Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches
ATE447765T1 (en) METHOD FOR SEMICONDUCTOR PRODUCTION WITH INTEGRATION OF A DISPOSABLE SPACER LAYER INTO THE INCREASED SOURCE/DRAIN PROCESSING
WO2009042981A3 (en) Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned si to sige conversion processes and structures formed thereby
WO2007110507A3 (en) Process for fabricating a field-effect transistor with self-aligned gates
CN110491837B (en) Internal L spacer for replacement gate flow
CN102903639A (en) MOS (Metal Oxide Semiconductor) transistor, substrate provided with stress layers and formation method of substrate provided with stress layer
CN101540286A (en) Method for production of semiconductor device
JP2008300662A (en) Manufacturing method of semiconductor device
CN105097683A (en) Manufacture method of semiconductor device
TW200701339A (en) Method of fabricating a silicon-on-insulator structure
CN104124142B (en) A kind of semiconductor devices and its manufacturing method
CN103378151B (en) A kind of silicon germanium structure reducing load effect and forming method thereof
CN105355597B (en) Utilize the production method of the cmos device of stress memory effect