CN105355597B

CN105355597B - Utilize the production method of the cmos device of stress memory effect

Info

Publication number: CN105355597B
Application number: CN201410416185.4A
Authority: CN
Inventors: 于书坤; 韦庆松
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-08-19
Filing date: 2014-08-19
Publication date: 2018-10-23
Anticipated expiration: 2034-08-19
Also published as: CN105355597A

Abstract

This application provides a kind of production methods of the cmos device using stress memory effect.The production method includes：Fleet plough groove isolation structure is set in the semiconductor substrate；Gate structure, the hard mask layer on gate structure, the offset side wall on gate structure sidewall are formed on NMOS area and the areas PMOS；On the exposed surface of semiconductor substrate, tensile stress layer is set on the exposed surface of hard mask layer and on the exposed surface of offset side wall；Tensile stress floor positioned at the areas PMOS is performed etching, to form the first stress side wall in the exposed sides of the offset side wall in the areas PMOS；The position of source area the to be formed and drain region setting SiGe portion in the areas PMOS；And the tensile stress layer of NMOS area is performed etching, to form the second stress side wall in the exposed sides of the offset side wall of NMOS area.NMOS area tensile stress layer is heat-treated using the high heat in SiGe portion setting up procedure, enhances stress memory effect.

Description

Utilize the production method of the cmos device of stress memory effect

Technical field

This application involves technical field of manufacturing semiconductors, in particular to a kind of CMOS using stress memory effect The production method of device.

Background technology

With the rapid development of semiconductor fabrication, semiconductor devices is in order to reach higher arithmetic speed, bigger Data storage capacity and more functions, semiconductor devices develop towards higher component density, higher integrated level direction. Therefore, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistor Grid become increasingly thinner and length becomes more shorter than previous.However, the change in size of grid can influence semiconductor devices Electric property, currently, mainly improving performance of semiconductor device by controlling carrier mobility.One of the technology is critical to Element is the stress in controlling transistor raceway groove.Such as suitable control stress, improve the carrier (electricity in n- channel transistors Son, the hole in p- channel transistors) mobility, driving current can be improved.Wherein, in cmos device channel direction (longitudinal) on, tensile stress is beneficial to NMOS electron mobilities, and compression is beneficial to PMOS hole mobilities；In ditch Tensile stress in road width direction (transverse) is beneficial to the carrier mobility of NMOS and PMOS device, and vertical The compression in channel plane direction (out-of-plane) is beneficial to NMOS device electron mobility, and tensile stress is then to PMOS device Mobility is beneficial.

Stress memory effect (SMT, Stress memorization technique) is a kind of CMOS technology introducing stress Method, technological process is：Cvd silicon oxide and silicon nitride after forming the gate structure with dummy poly, side wall, Then the silicon nitride is made annealing treatment, generates heat between silicon nitride, gate structure, raceway groove and side wall in annealing process Stress and planted agent's stress effect, these stress can be remembered in the dummy poly and raceway groove in gate structure, in the raceway groove sides NMOS To will produce tensile stress；It completes to remove the silicon nitride after annealing, but the tensile stress of NMOS channel directions is still remembered, To influence the carrier mobility of NMOS device.

But in characteristic size for 28nm and in the cmos device manufacture craft of lower node, stress memory effect exists NMOS area is generally difficult to reach the set goal, the main cause generally smaller, stressor layers because of the stress layer thickness of NMOS area Need to remove the performance for affecting stress memory effect with bigger than normal at a distance from raceway groove and dummy poly, but dummy poly Removal be difficult to avoid that.Therefore, it is necessary to technical staff to solve the above problems from first two reason, but the prior art is still The technical solution of the above problem is so efficiently solved without proposition.

Invention content

The application is intended to provide a kind of production method of the cmos device using stress memory effect, to solve the prior art The problem of stress memory effect of middle NMOS area is difficult to play.

To achieve the goals above, it according to the one side of the application, provides a kind of using stress memory effect The production method of cmos device, the production method include：Fleet plough groove isolation structure is arranged in step S1 in the semiconductor substrate, profit NMOS area and the areas PMOS are isolated with fleet plough groove isolation structure；Step S2 forms gate structure, position on NMOS area and the areas PMOS In the hard mask layer on gate structure, the offset side wall on gate structure sidewall；Step S3, in the exposed of semiconductor substrate On surface, tensile stress layer is set on the exposed surface of hard mask layer and on the exposed surface of offset side wall；Step S4, to being located at The tensile stress floor in the areas PMOS performs etching, to form the first stress side wall in the exposed sides of the offset side wall in the areas PMOS；Step Rapid S5, the position of source area the to be formed and drain region setting SiGe portion in the areas PMOS；And step S6, to the tensile stress of NMOS area Layer performs etching, to form the second stress side wall in the exposed sides of the offset side wall of NMOS area.

Further, above-mentioned steps S5 includes：Step S51 performs etching the exposed substrate in the areas PMOS, is formed Sigma type grooves, step S52 carry out the epitaxial growth of silicon germanium material in sigma type grooves, form SiGe portion.

Further, above-mentioned steps S51 includes：Dry etching is carried out to the exposed substrate in the areas PMOS, forms the first ditch Slot, the preferably etching gas of dry etching are selected from CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂And CH₄In one Kind is a variety of；Wet etching is carried out to the inner wall of first groove, forms sigma type grooves, the etching liquid of wet etching is organic Alkali and/or inorganic alkali solution.

Further, the reactant of above-mentioned epitaxial growth includes silicon source gas and ge source gas, silicon source gas SiH₄、 SiH₂Cl₂Or Si₂H₆, ge source gas is GeH₄。

Further, in above-mentioned epitaxial process, maximum temperature is 800~950 DEG C, and minimum temperature is 500~650 ℃。

Further, the total time of above-mentioned epitaxial growth is 10~120min, duration of maximum temperature is 10~ 300s。

Further, above-mentioned steps S3 forms tensile stress layer using chemical vapour deposition technique.

Further, above-mentioned tensile stress layer is silicon nitride layer or doped silicon nitride layer, the impurity member in doped silicon nitride layer Element is boron or phosphorus.

Further, the etching of above-mentioned steps S4 and above-mentioned steps S6 use dry etching, the preferably etching of dry etching Gas is selected from CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂And CH₄In it is one or more.

Further, the thickness of above-mentioned offset side wall is 3~10nm.

Further, the thickness of above-mentioned tensile stress layer is 5~35nm.

Further, above-mentioned offset side wall is silicon nitride layer.

Further, above-mentioned production method further includes in the first stress side wall and the second stress side wall after step S6 Main side wall is set in exposed sides, and preferably main side wall is the alternating layer of silicon nitride layer or silicon oxide layer and silicon nitride layer.

Using the technical solution of the application, SiGe portion is set in step s 5, and when the setting up procedure in SiGe portion needs long Between heat treatment process, therefore, the application utilizes the high heat that generates for a long time in SiGe portion setting up procedure to answer NMOS area Power layer is heat-treated, and to generate thermal stress and internal stress between gate structure, tensile stress layer and offset side wall, and is led to It crosses tensile stress layer tensile stress is transferred in the raceway groove of NMOS area, forms stress memory effect；And simultaneously because in the areas PMOS Stressor layers have been completed etching, therefore the heat treatment process will not have an impact the tensile stress in the areas PMOS；Above process profit The heat caused by SiGe portion forming process is heat-treated NMOS area tensile stress layer, instead of in the prior art to answering The step of power layer is made annealing treatment has saved the cost of manufacture of device；In addition, be formed by tensile stress layer step S6 quarter It can be used as side wall after erosion, and then also save the manufacture craft of side wall, while it is to carve in the prior art to also eliminate The oxide layer that etching off is arranged except tensile stress layer, and using tensile stress layer as a part for side wall, there is no need in subsequent technique In the tensile stress layer is separately provided, and then the thickness of tensile stress layer can be made to be increased in a limited space, into one Step ground enhancing stress memory effect；Simultaneously as only interval offsets side wall between tensile stress layer and gate structure, therefore opens and answer The spacing of power layer and raceway groove reduces, and then improves the effect of stress memory effect.

Description of the drawings

The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：

Fig. 1 shows the flow signal of the production method of the cmos device provided by the present application using stress memory effect Figure；

Fig. 2 to Figure 10 shows the cross-sectional view for the chip for implementing to be obtained after each step shown in Fig. 1；

Fig. 2 shows the cross-sectional views after setting fleet plough groove isolation structure in the semiconductor substrate；

Fig. 3 shows that the cross-section structure after forming gate structure and hard mask layer in semiconductor substrate shown in Fig. 2 shows It is intended to；

Fig. 4 shows the cross-sectional view formed on gate structure sidewall shown in Fig. 3 after offset side wall；

Fig. 5 shows on the exposed surface of semiconductor substrate shown in Fig. 4, on the exposed surface of hard mask layer and partially Move the cross-sectional view after setting tensile stress layer on the exposed surface of side wall；

Fig. 6 shows the offset side wall performed etching to the tensile stress floor shown in fig. 5 positioned at the areas PMOS in the areas PMOS The cross-sectional view after the first stress side wall is formed in exposed sides；

Fig. 7 is shown using the gate structure of PMOS areas shown in Fig. 6, offset side wall and the first stress side wall as mask, right The exposed semiconductor substrate in the areas PMOS performs etching, and forms the cross-sectional view after sigma type grooves；

Fig. 8 show in sigma type grooves shown in Fig. 7 carry out silicon germanium material be epitaxially-formed SiGe portion after Cross-sectional view；

Fig. 9 show to the tensile stress layer of NMOS area shown in Fig. 8 perform etching NMOS area offset side wall it is exposed The cross-sectional view after the second stress side wall is formed on side；And

Figure 10, which is shown, is arranged main side wall in the exposed sides of the first stress side wall shown in Fig. 9 and the second stress side wall Cross-sectional view afterwards.

Specific implementation mode

It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field The identical meanings of understanding.

It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative Be also intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.

For ease of description, herein can with use space relative terms, as " ... on ", " in ... top ", " ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure Except different direction in use or operation.For example, if the device in attached drawing is squeezed, it is described as " in other devices It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction " Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and " in ... lower section " two kinds of orientation.The device can also other different modes positioning (be rotated by 90 ° or be in other orientation), and And respective explanations are made to the opposite description in space used herein above.

As background technology is introduced, cause stress layer thickness inclined since the spacing of NMOS area is smaller in the prior art Small and stressor layers stressor layers bigger than normal at a distance from raceway groove, and then stress memory effect is caused to be generally difficult to reach pre- in NMOS area The target of phase, in order to solve defect as above, present applicant proposes a kind of making sides of the cmos device using stress memory effect Method.

Fig. 1 shows the flow diagram of the production method, which includes：Step S1, in semiconductor substrate 100 Middle setting fleet plough groove isolation structure 101, NMOS area I and the areas PMOS II are isolated using fleet plough groove isolation structure 101；Step S2, Gate structure 200 is formed on NMOS area I and the areas PMOS II, the hard mask layer 300 on gate structure 200, is located at grid Offset side wall 400 on 200 side wall of structure；Step S3, on the exposed surface of semiconductor substrate 100, hard mask layer 300 it is naked Reveal on surface and be arranged on the exposed surface of offset side wall 400 tensile stress layer 500；Step S4, to positioned at the areas PMOS II Stressor layers 500 perform etching, to form the first stress side wall 501 in the exposed sides of the offset side wall 400 in the areas PMOS II；Step Rapid S5, the position of II source area the to be formed and drain region setting SiGe portion 600 in the areas PMOS；And step S6, to NMOS area I Tensile stress layer 500 performs etching, to form the second stress side wall 502 in the exposed sides of the offset side wall 400 of NMOS area I.

SiGe portion 600 is arranged in above-mentioned production method in step s 5, and the setting up procedure in SiGe portion 600 needs for a long time Heat treatment process, therefore, the application utilizes the high heat that generates for a long time in 600 setting up procedure of SiGe portion to open NMOS area I Stressor layers 500 are heat-treated, to generate thermal stress between gate structure 200, tensile stress layer 500 and offset side wall 400 And internal stress, and tensile stress is transferred in the raceway groove of NMOS area I by tensile stress layer 500, form stress memory effect；And Simultaneously because the tensile stress floor 500 in the areas PMOS II has been completed etching, therefore the heat treatment process answers opening for the areas PMOS II Power will not have an impact；The above process is using heat caused by 600 forming process of SiGe portion to I tensile stress layer 500 of NMOS area It is heat-treated, instead of the step of being made annealing treatment in the prior art to tensile stress layer 500, has saved being fabricated to for device This；In addition, being formed by tensile stress layer 500 can use after the etching of step S6 as side wall, and then also save side The manufacture craft of wall, while the oxide layer being arranged in the prior art for etching removal tensile stress layer 500 is also eliminated, and will open A part of the stressor layers 500 as side wall there is no need to which the tensile stress layer 500 is separately provided in the subsequent process, and then is having The thickness of tensile stress layer 500 can be made to be increased in the space of limit, to further enhance stress memory effect；Meanwhile Since only interval offsets side wall 400 between tensile stress layer 500 and gate structure 200, between tensile stress layer 500 and raceway groove Away from reduction, and then improve the effect of stress memory effect.

Now, the illustrative embodiments according to the application are more fully described with reference to the accompanying drawings.However, these are exemplary Embodiment can be implemented by many different forms, and should not be construed to be limited solely to embodiment party set forth herein Formula.It should be understood that thesing embodiments are provided so that disclosure herein is thoroughly and complete, and these are shown The design of example property embodiment is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer With the thickness in region, and make that identical device is presented with like reference characters, thus description of them will be omitted.

First, fleet plough groove isolation structure 101 shown in Fig. 2 is set in semiconductor substrate 100, and using the shallow trench every Semiconductor substrate 100 is isolated into NMOS area I and the areas PMOS II shown in Fig. 2 from structure 101.Above-mentioned semiconductor substrate 100 Material can be the conventional semiconductor materials such as monocrystalline silicon, polysilicon, amorphous silicon；The formation of above-mentioned fleet plough groove isolation structure 101 Process is implemented using the ordinary skill in the art.

Then gate structure 200 is formed in NMOS area I shown in Fig. 2 and the areas PMOS II, on gate structure 200 Hard mask layer 300, the offset side wall 400 on 200 side wall of gate structure, obtain the chip with cross-section structure shown in Fig. 4. As recorded in background technology, above-mentioned gate structure 200 can be dummy poly gate structure, and then be subsequently formed gold Belong to grid, which includes the insulating layer and dummy poly successively far from semiconductor substrate 100.It below will be right The above process illustrates, which includes：

Oxide skin(coating) 201 is set gradually in semiconductor substrate 100 shown in Fig. 2, and (for example the oxide is by silicon oxide layer It is formed with the oxide skin(coating) with high-k, wherein hafnium oxide, oxygen may be used in the oxide skin(coating) with high-k Change zirconium etc.), dummy poly layer 202, silicon nitride layer (as hard mask layer 300) and to silicon nitride layer, dummy poly layer 202 and oxygen Compound layer 201 performs etching, and forms gate structure 200 and hard mask layer 300 shown in Fig. 3；Semiconductor lining shown in Fig. 3 The alternating knot of deposited silicon nitride or silica and silicon nitride on the exposed surface at bottom 100 and the exposed surface of hard mask layer 300 Structure, and the silicon nitride or alternating structure are performed etching, form offset side wall 400 shown in Fig. 4.It should be noted that After the formation of above-mentioned offset side wall 400, for the threshold voltage of adjusting device, LDD injections, this field can be carried out to substrate Technical staff implements the technique with reference to the prior art, and details are not described herein.

Then, on the exposed surface of semiconductor substrate 100 shown in Fig. 4, on the exposed surface of hard mask layer 300 and Tensile stress layer 500 is set on the exposed surface of offset side wall 400, forms the chip with cross-section structure shown in Fig. 5.The step is excellent Choosing forms tensile stress layer 500, the process conditions of chemical vapor deposition therein, people in the art using chemical vapour deposition technique Member can refer to the prior art and implement.It is preferred that above-mentioned tensile stress layer 500 is silicon nitride layer or doped silicon nitride layer, further preferably Impurity element in above-mentioned doped silicon nitride layer is boron or phosphorus.Those skilled in the art can be according to actual process design alternative The concentration of the boron or phosphorus that are adulterated in doped silicon nitride layer, details are not described herein.

In order to reduce the distance between tensile stress layer 500 and raceway groove, the thickness of preferably above-mentioned offset side wall 400 is the application 3~10nm so that spacing between tensile stress layer 500 and gate structure 200, tensile stress layer 500 and raceway groove be 3~ 10nm；And spacing bias side wall 400, germanium silicon side wall, main side wall between tensile stress layer 500 and gate structure 200 in the prior art 700, cause the spacing between tensile stress layer 500 and raceway groove between 15~30nm, it can be seen that, tensile stress layer 500 and raceway groove Between spacing be obviously reduced, and then be beneficial to the performance of stress memory effect.

In addition, as previously described due to only spacing bias side wall 400 between tensile stress layer 500 and gate structure 200, and it is existing Tensile stress layer 500 is set again after provided with offset side wall 400, germanium silicon side wall, main side wall 700 in technology, leads to tensile stress The thickness of layer 500 is smaller, and the application forms one of the second stress side wall 502 as side wall after etching tensile stress layer 500 Behind part, increases the thickness of tensile stress layer 500 under the premise of not influencing side wall integral thickness, reduce follow-up main side wall 700 Thickness, and then the performance of stress memory effect is improved, therefore the thickness of preferably above-mentioned tensile stress layer 500 is 5~35nm.

After the making for completing tensile stress layer 500, the tensile stress floor 500 shown in fig. 5 positioned at the areas PMOS II is carried out Etching, forms the first stress side wall 501 shown in fig. 6 in the exposed sides of the offset side wall 400 in the areas PMOS II.The process is first First photoresist layer is set on tensile stress layer 500, the photoresist in the areas PMOS II is then removed, to being located under the protection of photoresist The tensile stress floor 500 in the areas PMOS II performs etching, and retains the tensile stress layer 500 of NMOS area I, and then in the offset in the areas PMOS II The first stress side wall 501 is formed in the exposed sides of side wall 400, which can be as a part for side wall. Above-mentioned etching process uses dry etching, described dry when using silicon nitride layer or doped silicon nitride layer as tensile stress layer 500 The etching gas of method etching preferably uses CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂And CH₄In one kind or It is a variety of, to realize the etching to tensile stress layer 500.

SiGe portion 600 shown in Fig. 8 is arranged in the position of II source area to be formed of the areas PMOS and drain region shown in Fig. 6. The setting in above-mentioned SiGe portion 600 can improve the compression in the areas PMOS II, and then improve the performance of PMOS transistor.

The forming process in the SiGe portion 600 includes the following steps：

It is mask with the gate structure 200 of PMOS areas shown in Fig. 6 II, offset side wall 400 and the first stress side wall 501, it is right The exposed semiconductor substrate 100 in the areas PMOS II performs etching, and forms sigma types groove 600 ' shown in Fig. 7.The etching process It can carry out step by step, such as：Dry etching is carried out to the exposed substrate in the areas PMOS II, forms first groove, preferably dry method The etching gas of etching is selected from CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂And CH₄In it is one or more；

Then wet etching is carried out to the inner wall of first groove, forms sigma types groove 600 ' shown in Fig. 7, the wet method The etching liquid of etching is organic base and/or inorganic alkali solution, and above-mentioned wet etching has the silicon materials etch rate of different crystal faces It is variant, therefore the bowl-shape first groove that dry etching is formed is etched into hexagonal sigma types groove 600 '.

In addition above-mentioned sigma types groove 600 ' can also be formed using following methods：It uses first and is dry-etched in grid The opening that depth is 3~30nm is formed between structure 200；Then the opening is made annealing treatment, makes the bottom and side of opening Wall becomes round and smooth, is preferably passed through inert gas or hydrogen into annealing chamber in the annealing process, avoids the inner wall of opening It is aoxidized；Then the opening is continued to etch using wet etching, due to the bottom and side by annealing after-opening Wall becomes round and smooth, therefore can form sigma types groove 600 ' when use wet etching；Sigma type grooves shown in Fig. 7 The epitaxial growth that silicon germanium material is carried out in 600 ', forms SiGe portion 600 shown in Fig. 8.

The reactant of above-mentioned epitaxial growth includes silicon source gas and ge source gas, and preferably above-mentioned silicon source gas is SiH₄、 SiH₂Cl₂Or Si₂H₆, preferably above-mentioned ge source gas is GeH₄.Certainly, in order to avoid semiconductor substrate 100 is aoxidized, preferably logical The protective gas such as hydrogen, nitrogen can also be passed through while entering above-mentioned reactant.

Above-mentioned epitaxial growth may be used molecular beam epitaxy (MBE), ultra-high vacuum CVD (UHV/CVD), often The process implementings such as pressure chemical vapor deposition (APCVD) and rpcvd (RPCVD).Wherein, ensureing that SiGe is normal Under the premise of epitaxial growth, in order to provide enough heats to tensile stress layer 500, preferably in epitaxial process, maximum temperature It it is 800~950 DEG C, minimum temperature is 500~650 DEG C；It is preferred that the total time of epitaxial growth is 10~120min, further preferably The duration of maximum temperature is 10~300s.No matter any side used it can be seen from the forming process in above-mentioned SiGe portion 600 Formula forms SiGe portion 600, will produce high temperature, and then generates heat between gate structure 200, tensile stress layer 500 and side wall and answer Power and internal stress, and be transferred in the raceway groove of NMOS area I by 500 tensile stress of tensile stress layer, form stress memory effect.

After the making for completing above-mentioned SiGe portion 600, the tensile stress layer 500 of NMOS area I shown in Fig. 8 is performed etching, The second stress side wall 502 shown in Fig. 9 is formed in the exposed sides of the offset side wall 400 of NMOS area I.The etching process is with before State similar to the etching process of the tensile stress floor 500 in the areas PMOS II, details are not described herein.

After forming the second stress side wall 502, the first stress side wall 501 preferably shown in Fig. 9 and the second stress side Main side wall 700 shown in Fig. 10 is set in the exposed sides of wall 502.Utilize offset side wall 400, the first stress side wall 501 (or Two stress side walls 502) and above-mentioned formation main side wall 700 collectively as the application cmos device side wall.Above-mentioned main side wall 700 Setting up procedure can equally refer to the setting up procedure of the first stress side wall 501, for example first deposit corresponding 700 material of main side wall Material, then performs etching 700 material of main side wall of the areas PMOS II and NMOS area I, forms main side wall 700 shown in Fig. 10.On State the alternating layer that wall 700 material in main side is preferably silicon nitride or silicon oxide layer and silicon nitride layer.

Certainly, after completing above-mentioned technique, those skilled in the art can need according to the design of device into row metal The making of the making of silicide, metal interconnection structure etc., such as via, plug and metal wiring layer etc., the manufacture craft of use It can refer to the prior art.

It can be seen from the above description that the above-mentioned embodiment of the application realizes following technique effect：

1) SiGe portion is set in step s 5, and the setting up procedure in SiGe portion needs prolonged high-temperature heat treatment process, Therefore, the application is heat-treated tensile stress layer using the high temperature high heat generated for a long time in SiGe portion setting up procedure, from And thermal stress and internal stress are generated between gate structure, tensile stress layer and side wall, and passed tensile stress by tensile stress layer In the defeated raceway groove to NMOS area, stress memory effect is formed, and simultaneously because the tensile stress floor in the areas PMOS has been completed etching, It is no longer continuous film, therefore the heat treatment process not will produce any influence to the tensile stress in the areas PMOS；

2) above process is heat-treated tensile stress layer using heat caused by SiGe portion forming process, instead of existing There is the step of being made annealing treatment to tensile stress layer in technology, has saved the cost of manufacture of device；

3) being formed by tensile stress layer can use after the etching of step S6 as side wall, and then also save side wall Manufacture craft, while also eliminating the etching removal tensile stress layer of position in the prior art and the oxide layer that is arranged, and by tensile stress A part of the layer as side wall, there is no need to which the tensile stress layer is separately provided in the subsequent process, and then in a limited space The thickness of tensile stress layer can be made to be increased, to further enhance stress memory effect；

4) since only interval offsets side wall, the spacing of tensile stress layer and raceway groove between tensile stress layer and gate structure Reduce, and then improves the effect of stress memory effect.

5) technological process all in the above process is all that usual germanium silicon portion forms necessary step, is not increased any Technical process, it is thus only necessary to tensile stress layer be used to replace common neutral stress layer (being in special circumstances compressive stress layer) conduct Outside NMOS germanium silicon growth protective layers and adjusting germanium silicon growth temperature cooperation NMOS tensile stress demands, relatively traditional stress memory The PMOS area stress before stressor layers growth, stressor layers annealing, stressor layers removal and its optional annealing necessary to technology Layer photoetching, etching technics all no longer need, therefore greatly reduce production cost.

The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.

Claims

1. a kind of production method of cmos device using stress memory effect, which is characterized in that the production method includes：

Step S1, is arranged fleet plough groove isolation structure in the semiconductor substrate, and NMOS is isolated using the fleet plough groove isolation structure Area and the areas PMOS；

Step S2 forms gate structure, the hard mask on the gate structure on the NMOS area and the areas PMOS Layer, the offset side wall on the gate structure sidewall；

Step S3, on the exposed surface of the semiconductor substrate, on the exposed surface of the hard mask layer and the offset Tensile stress layer is set on the exposed surface of side wall；

Step S4 performs etching the tensile stress floor positioned at the areas PMOS, in the offset side wall in the areas PMOS The first stress side wall is formed in exposed sides；

Step S5, the position of source area to be formed and drain region setting SiGe portion, the setting in the SiGe portion in the areas PMOS Process includes heat treatment process, and using the heat generated in the heat treatment process for forming the SiGe portion to NMOS area Tensile stress layer is heat-treated；And

Step S6 performs etching the tensile stress layer of the NMOS area, in the exposed of the offset side wall of the NMOS area The second stress side wall is formed on side.

2. manufacturing method according to claim 1, which is characterized in that the step S5 includes：

Step S51 performs etching the exposed substrate in the areas PMOS, forms sigma type grooves,

Step S52 carries out the epitaxial growth of silicon germanium material in the sigma types groove, forms the SiGe portion.

3. production method according to claim 2, which is characterized in that the step S51 includes：

Dry etching is carried out to the exposed substrate in the areas PMOS, forms first groove, the etching of the preferably described dry etching Gas is selected from CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂And CH₄In it is one or more；

Wet etching is carried out to the inner wall of the first groove, forms sigma type grooves, the etching liquid of the wet etching is to have Machine alkali and/or inorganic alkali solution.

4. production method according to claim 3, which is characterized in that the reactant of the epitaxial growth includes silicon source gas With ge source gas, the silicon source gas is SiH₄、SiH₂Cl₂Or Si₂H₆, the ge source gas is GeH₄。

5. production method according to claim 3, which is characterized in that in the epitaxial process, maximum temperature 800 ~950 DEG C, minimum temperature is 500~650 DEG C.

6. production method according to claim 5, which is characterized in that the total time of the epitaxial growth be 10~ The duration of 120min, the maximum temperature are 10~300s.

7. manufacturing method according to claim 1, which is characterized in that the step S3 is formed using chemical vapour deposition technique The tensile stress layer.

8. production method according to claim 7, which is characterized in that the tensile stress layer is silicon nitride layer or doping nitridation Silicon layer, the impurity element in the doped silicon nitride layer are boron or phosphorus.

9. production method according to claim 8, which is characterized in that the etching of the step S4 and the step S6 use The etching gas of dry etching, the preferably described dry etching is selected from CF₄、CHF₃、CH₂F₂、CH₃F、O₂、HCl、HBr、SO₂、He、H₂ And CH₄In it is one or more.

10. manufacturing method according to claim 1, which is characterized in that the thickness of the offset side wall is 3~10nm.

11. manufacturing method according to claim 1, which is characterized in that the thickness of the tensile stress layer is 5~35nm.

12. manufacturing method according to claim 1, which is characterized in that the offset side wall is silicon nitride layer.

13. manufacturing method according to claim 1, which is characterized in that the production method is gone back after the step S6 Include setting main side wall, the preferably described main side wall in the exposed sides of the first stress side wall and the second stress side wall For silicon nitride layer or the alternating layer of silicon oxide layer and silicon nitride layer.