FR2799307B1 - Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication - Google Patents

Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication

Info

Publication number
FR2799307B1
FR2799307B1 FR9912308A FR9912308A FR2799307B1 FR 2799307 B1 FR2799307 B1 FR 2799307B1 FR 9912308 A FR9912308 A FR 9912308A FR 9912308 A FR9912308 A FR 9912308A FR 2799307 B1 FR2799307 B1 FR 2799307B1
Authority
FR
France
Prior art keywords
massive
architectures
itself
manufacturing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9912308A
Other languages
English (en)
Other versions
FR2799307A1 (fr
Inventor
Daniel Bois
Thomas Skotnicki
Malgorzata Jurczak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Priority to FR9912308A priority Critical patent/FR2799307B1/fr
Priority to EP00966241A priority patent/EP1218942A1/fr
Priority to PCT/FR2000/002710 priority patent/WO2001026160A1/fr
Publication of FR2799307A1 publication Critical patent/FR2799307A1/fr
Application granted granted Critical
Publication of FR2799307B1 publication Critical patent/FR2799307B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
FR9912308A 1999-10-01 1999-10-01 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication Expired - Fee Related FR2799307B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9912308A FR2799307B1 (fr) 1999-10-01 1999-10-01 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication
EP00966241A EP1218942A1 (fr) 1999-10-01 2000-09-29 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, et procede de fabrication
PCT/FR2000/002710 WO2001026160A1 (fr) 1999-10-01 2000-09-29 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, et procede de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9912308A FR2799307B1 (fr) 1999-10-01 1999-10-01 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication

Publications (2)

Publication Number Publication Date
FR2799307A1 FR2799307A1 (fr) 2001-04-06
FR2799307B1 true FR2799307B1 (fr) 2002-02-15

Family

ID=9550508

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9912308A Expired - Fee Related FR2799307B1 (fr) 1999-10-01 1999-10-01 Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication

Country Status (3)

Country Link
EP (1) EP1218942A1 (fr)
FR (1) FR2799307B1 (fr)
WO (1) WO2001026160A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142526A1 (en) * 2001-03-30 2002-10-03 International Business Machines Corporation Structures and methods to minimize plasma charging damage in silicon on insulator devices
US7078298B2 (en) * 2003-05-20 2006-07-18 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process
US7015147B2 (en) * 2003-07-22 2006-03-21 Sharp Laboratories Of America, Inc. Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
US6964911B2 (en) * 2003-09-23 2005-11-15 Freescale Semiconductor, Inc. Method for forming a semiconductor device having isolation regions
FR2865850B1 (fr) 2004-02-03 2006-08-04 St Microelectronics Sa Procede de realisation d'un transistor a effet de champ et transistor ainsi obtenu
US7256077B2 (en) * 2004-05-21 2007-08-14 Freescale Semiconductor, Inc. Method for removing a semiconductor layer
JP4759967B2 (ja) * 2004-10-01 2011-08-31 セイコーエプソン株式会社 半導体装置の製造方法
JP2006156867A (ja) 2004-12-01 2006-06-15 Seiko Epson Corp 半導体基板の製造方法および半導体装置の製造方法
WO2007003220A1 (fr) * 2005-06-30 2007-01-11 Freescale Semiconductor, Inc Procédé de formation d'une structure semi-conductrice
US20070194353A1 (en) * 2005-08-31 2007-08-23 Snyder John P Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof
FR2897202B1 (fr) * 2006-02-08 2008-09-12 St Microelectronics Crolles 2 Transistor mos a barriere de schottky sur film semi-conducteur entierement appauvri et procede de fabrication d'un tel transistor.
US8304301B2 (en) * 2009-11-18 2012-11-06 International Business Machines Corporation Implant free extremely thin semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020582A (ja) * 1983-07-14 1985-02-01 Nec Corp Ｍｉｓトランジスタ及びその製造方法
JP3484726B2 (ja) * 1992-07-16 2004-01-06 富士通株式会社 半導体装置およびその製造方法
US5405795A (en) * 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact
FR2750534B1 (fr) * 1996-06-27 1998-08-28 Commissariat Energie Atomique Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes
US5773331A (en) * 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts

Also Published As

Publication number Publication date
FR2799307A1 (fr) 2001-04-06
EP1218942A1 (fr) 2002-07-03
WO2001026160A1 (fr) 2001-04-12

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070629