FR2750534B1 - Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes - Google Patents

Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes

Info

Publication number
FR2750534B1
FR2750534B1 FR9608007A FR9608007A FR2750534B1 FR 2750534 B1 FR2750534 B1 FR 2750534B1 FR 9608007 A FR9608007 A FR 9608007A FR 9608007 A FR9608007 A FR 9608007A FR 2750534 B1 FR2750534 B1 FR 2750534B1
Authority
FR
France
Prior art keywords
transistor
contacts
self
producing
field isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9608007A
Other languages
English (en)
Other versions
FR2750534A1 (fr
Inventor
Simon Deleonibus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR9608007A priority Critical patent/FR2750534B1/fr
Priority to JP10502458A priority patent/JP2000514241A/ja
Priority to US09/147,438 priority patent/US6150241A/en
Priority to PCT/FR1997/001146 priority patent/WO1997050118A1/fr
Priority to EP97930599A priority patent/EP0958602A1/fr
Publication of FR2750534A1 publication Critical patent/FR2750534A1/fr
Application granted granted Critical
Publication of FR2750534B1 publication Critical patent/FR2750534B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
FR9608007A 1996-06-27 1996-06-27 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes Expired - Fee Related FR2750534B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR9608007A FR2750534B1 (fr) 1996-06-27 1996-06-27 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes
JP10502458A JP2000514241A (ja) 1996-06-27 1997-06-26 自己整合されたコンタクトおよびフィールド絶縁物を伴ったトランジスタおよび該トランジスタのための製造プロセス
US09/147,438 US6150241A (en) 1996-06-27 1997-06-26 Method for producing a transistor with self-aligned contacts and field insulation
PCT/FR1997/001146 WO1997050118A1 (fr) 1996-06-27 1997-06-26 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes
EP97930599A EP0958602A1 (fr) 1996-06-27 1997-06-26 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9608007A FR2750534B1 (fr) 1996-06-27 1996-06-27 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes

Publications (2)

Publication Number Publication Date
FR2750534A1 FR2750534A1 (fr) 1998-01-02
FR2750534B1 true FR2750534B1 (fr) 1998-08-28

Family

ID=9493478

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9608007A Expired - Fee Related FR2750534B1 (fr) 1996-06-27 1996-06-27 Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes

Country Status (5)

Country Link
US (1) US6150241A (fr)
EP (1) EP0958602A1 (fr)
JP (1) JP2000514241A (fr)
FR (1) FR2750534B1 (fr)
WO (1) WO1997050118A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656779B1 (en) * 1998-10-06 2003-12-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor apparatus having semiconductor circuits made of semiconductor devices, and method of manufacture thereof
FR2799307B1 (fr) * 1999-10-01 2002-02-15 France Telecom Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication
FR2810157B1 (fr) 2000-06-09 2002-08-16 Commissariat Energie Atomique Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene
FR2839202A1 (fr) * 2002-04-26 2003-10-31 St Microelectronics Sa Zone active de circuit integre mos
JP2004165566A (ja) * 2002-11-15 2004-06-10 Nec Corp せり上げ素子分離構造を有する半導体装置及びその製造方法
US6980467B2 (en) * 2002-12-09 2005-12-27 Progressant Technologies, Inc. Method of forming a negative differential resistance device
JP2006222101A (ja) 2003-01-10 2006-08-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
CN1328763C (zh) * 2003-04-29 2007-07-25 茂德科技股份有限公司 具有局部蚀刻栅极的半导体结构及其制作方法
KR100753098B1 (ko) * 2004-12-28 2007-08-29 주식회사 하이닉스반도체 채널길이를 증가시킨 반도체 소자 및 그의 제조 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4902641A (en) * 1987-07-31 1990-02-20 Motorola, Inc. Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure
JP2510710B2 (ja) * 1988-12-13 1996-06-26 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ
JP2941908B2 (ja) * 1989-07-31 1999-08-30 キヤノン株式会社 薄膜トランジスタ及びその製造方法並びにそれを有する装置
US5874341A (en) * 1996-10-30 1999-02-23 Advanced Micro Devices, Inc. Method of forming trench transistor with source contact in trench
JP3484726B2 (ja) * 1992-07-16 2004-01-06 富士通株式会社 半導体装置およびその製造方法
US5315144A (en) * 1992-09-18 1994-05-24 Harris Corporation Reduction of bipolar gain and improvement in snap-back sustaining voltage in SOI field effect transistor
JPH0714916A (ja) * 1993-06-22 1995-01-17 Nec Corp Ｍｏｓ電界効果トランジスタの分離構造およびその製造 方法
US5567966A (en) * 1993-09-29 1996-10-22 Texas Instruments Incorporated Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain
US5482871A (en) * 1994-04-15 1996-01-09 Texas Instruments Incorporated Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate
US5494837A (en) * 1994-09-27 1996-02-27 Purdue Research Foundation Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls
KR100253699B1 (ko) * 1996-06-29 2000-05-01 김영환 Soi소자 및 그 제조방법
US5801075A (en) * 1996-10-30 1998-09-01 Advanced Micro Devices, Inc. Method of forming trench transistor with metal spacers
JP3382840B2 (ja) * 1997-05-23 2003-03-04 シャープ株式会社 半導体装置の製造方法
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

Also Published As

Publication number Publication date
WO1997050118A1 (fr) 1997-12-31
US6150241A (en) 2000-11-21
EP0958602A1 (fr) 1999-11-24
FR2750534A1 (fr) 1998-01-02
JP2000514241A (ja) 2000-10-24

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130228