KR100940352B1 - 서로 다른 두께의 게이트 절연층들을 갖는 트랜지스터의 제조 방법 - Google Patents
서로 다른 두께의 게이트 절연층들을 갖는 트랜지스터의 제조 방법 Download PDFInfo
- Publication number
- KR100940352B1 KR100940352B1 KR1020047018365A KR20047018365A KR100940352B1 KR 100940352 B1 KR100940352 B1 KR 100940352B1 KR 1020047018365 A KR1020047018365 A KR 1020047018365A KR 20047018365 A KR20047018365 A KR 20047018365A KR 100940352 B1 KR100940352 B1 KR 100940352B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- gate insulating
- material layer
- insulating layers
- sacrificial material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/145,519 US6541321B1 (en) | 2002-05-14 | 2002-05-14 | Method of making transistors with gate insulation layers of differing thickness |
| US10/145,519 | 2002-05-14 | ||
| PCT/US2002/040500 WO2003098685A1 (en) | 2002-05-14 | 2002-12-17 | Method of making transistors with gate insulation layers of differing thickness |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040106546A KR20040106546A (ko) | 2004-12-17 |
| KR100940352B1 true KR100940352B1 (ko) | 2010-02-04 |
Family
ID=22513473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020047018365A Expired - Fee Related KR100940352B1 (ko) | 2002-05-14 | 2002-12-17 | 서로 다른 두께의 게이트 절연층들을 갖는 트랜지스터의 제조 방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6541321B1 (enExample) |
| EP (1) | EP1504470A1 (enExample) |
| JP (1) | JP2005526399A (enExample) |
| KR (1) | KR100940352B1 (enExample) |
| CN (1) | CN1310314C (enExample) |
| AU (1) | AU2002353166A1 (enExample) |
| WO (1) | WO2003098685A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004519090A (ja) * | 2000-08-07 | 2004-06-24 | アンバーウェーブ システムズ コーポレイション | 歪み表面チャネル及び歪み埋め込みチャネルmosfet素子のゲート技術 |
| WO2002103760A2 (en) * | 2001-06-14 | 2002-12-27 | Amberware Systems Corporation | Method of selective removal of sige alloys |
| KR20040077900A (ko) * | 2002-02-01 | 2004-09-07 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 고품질 산화물층 형성 방법 및 비휘발성 메모리 소자 |
| US6879007B2 (en) * | 2002-08-08 | 2005-04-12 | Sharp Kabushiki Kaisha | Low volt/high volt transistor |
| CN100521071C (zh) * | 2003-07-11 | 2009-07-29 | Nxp股份有限公司 | 一种半导体器件的制造方法及在这种方法中使用的装置 |
| DE602004024071D1 (de) * | 2003-07-11 | 2009-12-24 | Nxp Bv | Verfahren für das herstellen eines halbleiterbauelements |
| US20050112824A1 (en) * | 2003-11-26 | 2005-05-26 | Yu-Chang Jong | Method of forming gate oxide layers with multiple thicknesses on substrate |
| JP4040602B2 (ja) * | 2004-05-14 | 2008-01-30 | Necエレクトロニクス株式会社 | 半導体装置 |
| JP2006344634A (ja) * | 2005-06-07 | 2006-12-21 | Renesas Technology Corp | Cmos型半導体装置の製造方法および、cmos型半導体装置 |
| US7410874B2 (en) * | 2006-07-05 | 2008-08-12 | Chartered Semiconductor Manufacturing, Ltd. | Method of integrating triple gate oxide thickness |
| KR100853796B1 (ko) * | 2007-06-07 | 2008-08-25 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
| US20090065820A1 (en) * | 2007-09-06 | 2009-03-12 | Lu-Yang Kao | Method and structure for simultaneously fabricating selective film and spacer |
| US8232605B2 (en) * | 2008-12-17 | 2012-07-31 | United Microelectronics Corp. | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device |
| US8828834B2 (en) | 2012-06-12 | 2014-09-09 | Globalfoundries Inc. | Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process |
| US8975143B2 (en) | 2013-04-29 | 2015-03-10 | Freescale Semiconductor, Inc. | Selective gate oxide properties adjustment using fluorine |
| US9263270B2 (en) | 2013-06-06 | 2016-02-16 | Globalfoundries Inc. | Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918116A (en) * | 1994-11-30 | 1999-06-29 | Lucent Technologies Inc. | Process for forming gate oxides possessing different thicknesses on a semiconductor substrate |
| US6251747B1 (en) * | 1999-11-02 | 2001-06-26 | Philips Semiconductors, Inc. | Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0136935B1 (ko) * | 1994-04-21 | 1998-04-24 | 문정환 | 메모리 소자의 제조방법 |
| JP3194370B2 (ja) * | 1998-05-11 | 2001-07-30 | 日本電気株式会社 | 半導体装置とその製造方法 |
| JP2000003965A (ja) * | 1998-06-15 | 2000-01-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US6335262B1 (en) * | 1999-01-14 | 2002-01-01 | International Business Machines Corporation | Method for fabricating different gate oxide thicknesses within the same chip |
-
2002
- 2002-05-14 US US10/145,519 patent/US6541321B1/en not_active Expired - Lifetime
- 2002-12-17 CN CNB02828948XA patent/CN1310314C/zh not_active Expired - Fee Related
- 2002-12-17 WO PCT/US2002/040500 patent/WO2003098685A1/en not_active Ceased
- 2002-12-17 EP EP02790146A patent/EP1504470A1/en not_active Withdrawn
- 2002-12-17 JP JP2004506080A patent/JP2005526399A/ja active Pending
- 2002-12-17 AU AU2002353166A patent/AU2002353166A1/en not_active Abandoned
- 2002-12-17 KR KR1020047018365A patent/KR100940352B1/ko not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918116A (en) * | 1994-11-30 | 1999-06-29 | Lucent Technologies Inc. | Process for forming gate oxides possessing different thicknesses on a semiconductor substrate |
| US6251747B1 (en) * | 1999-11-02 | 2001-06-26 | Philips Semiconductors, Inc. | Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040106546A (ko) | 2004-12-17 |
| CN1310314C (zh) | 2007-04-11 |
| JP2005526399A (ja) | 2005-09-02 |
| WO2003098685A1 (en) | 2003-11-27 |
| CN1625803A (zh) | 2005-06-08 |
| EP1504470A1 (en) | 2005-02-09 |
| AU2002353166A1 (en) | 2003-12-02 |
| US6541321B1 (en) | 2003-04-01 |
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