KR920001625A - 표면적이 극대화된 실리콘층 및 그 제조방법 - Google Patents

표면적이 극대화된 실리콘층 및 그 제조방법 Download PDF

Info

Publication number
KR920001625A
KR920001625A KR1019900009260A KR900009260A KR920001625A KR 920001625 A KR920001625 A KR 920001625A KR 1019900009260 A KR1019900009260 A KR 1019900009260A KR 900009260 A KR900009260 A KR 900009260A KR 920001625 A KR920001625 A KR 920001625A
Authority
KR
South Korea
Prior art keywords
silicon layer
layer
insulating layer
silicon
forming
Prior art date
Application number
KR1019900009260A
Other languages
English (en)
Other versions
KR930008580B1 (ko
Inventor
김재갑
정인술
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019900009260A priority Critical patent/KR930008580B1/ko
Priority to US07/716,901 priority patent/US5149676A/en
Priority to JP3150549A priority patent/JP2519612B2/ja
Publication of KR920001625A publication Critical patent/KR920001625A/ko
Priority to US07/899,332 priority patent/US5304828A/en
Application granted granted Critical
Publication of KR930008580B1 publication Critical patent/KR930008580B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface

Abstract

내용 없음

Description

표면적이 극대화된 실리콘층 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의해 표면적을 증대시킨 실리콘층 표면을 촬영한 상태의 표면,
제3A도 내지 제3E도는 본 발명의 제1실시예를 따라 실리콘층을 형성하는 단계를 나타낸 단면도,
제4A도 내지 제4E도는 본 발명의 제2실시예를 따라 실리콘층을 형성하는 단계를 나타낸 단면도.

Claims (18)

  1. 상부에 소정의 배선 및 소자가 형성된 실리콘 기판을 가진 고집적 반도체 소자의 표면적이 극대화된 실리콘층 제조방법에 있어서, 상기 실리콘을 기판 상부에 제1절연층 및 제1실리콘층을 형성하는 단계와, 상기 제1실리콘층 상부에 제2절연층을 후에 핀홀이 발생될 수 있는 예정된 두께로 형성하는 단계와, 상기 제2절연층 상부에 제2실리콘층을 예정된 두께로 형성하여, 상기 제2실리콘층 하부에 제2절연층의 잔유층과 다수의 핀홀이 형성되도록 하는 단계와, 상기 제2실리콘층이 제2절연층의 잔유층보다 빠른 속도로 식각되게 하는 비율로 상기 제2실리콘층을 완전히 식각하고, 상기 핀홀에 의해 일부가 노출된 상기 제1실리콘층을 계속하여 상기 제2절연층의 잔유층이 일부 또는 완전히 제거된때까지 식각하여 상기 제1실리콘층에 다수의 홈을 형성하는 단계로 이루어져, 그로인하여 제1실리콘층의 표면이 그랜뉴레이트 형태로 이루어지게 하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  2. 제1항에 있어서, 상기의 제1실리콘층에 다수의 홈을 형성하는 단계후에, 제1실리콘층의 손상을 회복하기 위해 제1실리콘층 상부에 제3실리콘층을 소정 두께로 형성하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  3. 제1항 또는 제2항에 있어서, 상기 제1실리콘층, 제2실리콘층 및 제3실리콘층은 다결정 또는 아몰포스 실리콘층인 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  4. 제1항에 있어서, 상기 제1실리콘층 상부에 형성되는 제2절연층은 산화막으로 H2SO4와 H2O2혼합용액에서 5~30°A두께로 성장시켜 형성한 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  5. 제1항에 있어서, 상기 제2절연층은 가열로(Furnace)에서 O2개스와 고온조건에서 100~500°A정도 성장시킨 다음 건식식각으로 상기 산화막을 50~200°A으로 식각하여 형성하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  6. 제1항에 있어서, 상기 제1실리콘층 상부에 형성되는 제2절연층에 조밀한 결합을 만들기 위하여 제2절연층을 형성한후, 그 상부에 이온을 주입하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  7. 제1항에 있어서, 상기 제2실리콘층과 제2절연층의 식각단계는 5:1의 식각선택비율 이상으로 제2실리콘층이 제2절연층보다 식각속도가 빠르게한 건식식각으로 수행하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  8. 제7항에 있어서, 상기 제2실리콘층과 제2절연층을 동시에 건식식각할때 식각개스는 Cl2또는 SF6를 포함하는 혼합개스인 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  9. 제1항에 있어서, 상기의 제1실리콘층에 다수의 홈을 형성하는 단계후에, 제1실리콘층 상부의 제2절연층의 잔유층이 잔존하는 경우, 이를 십식식각으로 제거하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  10. 제1항의 제조방법에 의해 실리콘층의 표면이 그랜뉴레이트 형태로 형성된 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  11. 상부에 소정의 배선 및 소자가 형성된 실리콘 기판을 가진 고집적 반도체 소자의 표면적이 극대화된 실리콘층 제조방법에 있어서, 상기 실리콘을 기판 상부에 제1절연층 및 제1실리콘층을 형성하는 단계와, 상기 제1실리콘층 상부에 제2절연층을 소정두께 형성하고 이를 식각하여 다수의 홈이 형성된 상기 제2절연층의 잔유층 및 핀홀을 형성하는 단계와, 상기 제1실리콘층이 제2절연층의 잔유층보다 빠른 속도로 식각되게 하는 비율로 상기 핀홀에 의해 일부가 노출된 상기 제1실리콘층을 상기 제1절연층의 잔유층이 일부 또는 완전히 제거될때까지 식각하여 상기 제1실리콘층에 다수의 홈을 형성하는 단계로 이루어져, 그로인하여 제1실리콘층의 표면이 그랜뉴레이트형태로 이루어지게 하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  12. 제11항에 있어서, 상기 제1실리콘층에 다수의 홈을 형성하는 단계후에, 제1실리콘층의 손상을 회복하기 위해 제1실리콘층 상부에 제2실리콘층을 소정 두께로 형성하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  13. 제11항 또는 제12항에 있어서, 상기 제1실리콘층 및 제2실리콘층은 다결정 또는 아몰포스 실리콘층인 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  14. 제11항에 있어서, 상기 제2절연층은 산화막으로 가열로(Furnace)에서 O2개스와 고온조건에서 100~500°A정도 성장시켜 형성하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  15. 제11항에 있어서, 상기 제2절연층을 소정두께로 형성하는 단계후에, 상기 제2절연층에 조밀한 결함을 만들기 위하여 제2절연층을 형성한후 이온을 임플란트하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  16. 제11항에 있어서, 상기 제2절연층과 노출된 제1실리콘층의 식각단계는, 5:1의 식각선택비율 이상으로 제1실리콘층이 제2절연층보다 식각속도가 빠르게한 건식식각으로 수행하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  17. 제16항에 있어서, 상기 제2절연층과 노출된 제1실리콘층을 건식식각할때 식각개스는 Cl2또는 SF6를 포함하는 혼합개스인 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
  18. 제11항에 있어서, 상기의 제1실리콘층에 다수의 홈을 형성하는 단계후에, 잔존할수 있는 제1실리콘층을 상부의 제2절연층을 제거하기 위하여 습식식각으로 제2절연층을 제거하는 것을 포함하는 것을 특징으로 하는 표면적이 극대화된 실리콘층 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009260A 1990-06-22 1990-06-22 표면적이 극대화된 실리콘층 및 그 제조방법 KR930008580B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019900009260A KR930008580B1 (ko) 1990-06-22 1990-06-22 표면적이 극대화된 실리콘층 및 그 제조방법
US07/716,901 US5149676A (en) 1990-06-22 1991-06-18 Silicon layer having increased surface area and method for manufacturing
JP3150549A JP2519612B2 (ja) 1990-06-22 1991-06-21 表面積が極大化されたシリコン層の製造方法
US07/899,332 US5304828A (en) 1990-06-22 1992-06-16 Silicon layer having increased surface area and method for manufacturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900009260A KR930008580B1 (ko) 1990-06-22 1990-06-22 표면적이 극대화된 실리콘층 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR920001625A true KR920001625A (ko) 1992-01-30
KR930008580B1 KR930008580B1 (ko) 1993-09-09

Family

ID=19300409

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900009260A KR930008580B1 (ko) 1990-06-22 1990-06-22 표면적이 극대화된 실리콘층 및 그 제조방법

Country Status (3)

Country Link
US (2) US5149676A (ko)
JP (1) JP2519612B2 (ko)
KR (1) KR930008580B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100260486B1 (ko) * 1997-06-30 2000-08-01 김영환 반도체장치의전하저장전극형성방법
KR100427540B1 (ko) * 1997-06-25 2004-07-19 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930004110B1 (ko) * 1990-10-25 1993-05-20 현대전자산업 주식회사 표면적이 극대화된 도전층 제조방법
US5244842A (en) * 1991-12-17 1993-09-14 Micron Technology, Inc. Method of increasing capacitance by surface roughening in semiconductor wafer processing
USRE35420E (en) * 1991-02-11 1997-01-07 Micron Technology, Inc. Method of increasing capacitance by surface roughening in semiconductor wafer processing
KR920018987A (ko) * 1991-03-23 1992-10-22 김광호 캐패시터의 제조방법
KR940009616B1 (ko) * 1991-09-09 1994-10-15 금성일렉트론 주식회사 홀 캐패시터 셀 및 그 제조방법
US5213992A (en) * 1991-10-02 1993-05-25 Industrial Technology Research Institute Rippled polysilicon surface capacitor electrode plate for high density DRAM
US5350707A (en) * 1991-11-19 1994-09-27 Samsung Electronics Co., Ltd. Method for making a capacitor having an electrode surface with a plurality of trenches formed therein
KR960005246B1 (ko) * 1992-10-21 1996-04-23 현대전자산업주식회사 캐패시터의 저장전극 제조방법
JPH0774268A (ja) * 1993-07-07 1995-03-17 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
KR970005945B1 (ko) * 1993-08-09 1997-04-22 엘지반도체 주식회사 반도체 박막트랜지스터 제조방법
US5466626A (en) * 1993-12-16 1995-11-14 International Business Machines Corporation Micro mask comprising agglomerated material
US5972771A (en) 1994-03-11 1999-10-26 Micron Technology, Inc. Enhancing semiconductor structure surface area using HSG and etching
US5696014A (en) * 1994-03-11 1997-12-09 Micron Semiconductor, Inc. Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch
US5482882A (en) * 1994-03-18 1996-01-09 United Microelectronics Corporation Method for forming most capacitor using polysilicon islands
US5427974A (en) * 1994-03-18 1995-06-27 United Microelectronics Corporation Method for forming a capacitor in a DRAM cell using a rough overlayer of tungsten
US5492848A (en) * 1994-03-18 1996-02-20 United Microelectronics Corp. Stacked capacitor process using silicon nodules
US5482885A (en) * 1994-03-18 1996-01-09 United Microelectronics Corp. Method for forming most capacitor using poly spacer technique
US5512768A (en) * 1994-03-18 1996-04-30 United Microelectronics Corporation Capacitor for use in DRAM cell using surface oxidized silicon nodules
US5466627A (en) * 1994-03-18 1995-11-14 United Microelectronics Corporation Stacked capacitor process using BPSG precipitates
US5508542A (en) * 1994-10-28 1996-04-16 International Business Machines Corporation Porous silicon trench and capacitor structures
US5885882A (en) * 1995-07-18 1999-03-23 Micron Technology, Inc. Method for making polysilicon electrode with increased surface area making same
US5801104A (en) * 1995-10-24 1998-09-01 Micron Technology, Inc. Uniform dielectric film deposition on textured surfaces
US5650351A (en) * 1996-01-11 1997-07-22 Vanguard International Semiconductor Company Method to form a capacitor having multiple pillars for advanced DRAMS
US5808335A (en) * 1996-06-13 1998-09-15 Vanguard International Semiconductor Corporation Reduced mask DRAM process
US6013555A (en) * 1996-08-30 2000-01-11 United Microelectronics Corp. Process for rounding an intersection between an HSG-SI grain and a polysilicon layer
US6069053A (en) * 1997-02-28 2000-05-30 Micron Technology, Inc. Formation of conductive rugged silicon
US5937314A (en) 1997-02-28 1999-08-10 Micron Technology, Inc. Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
US6066539A (en) 1997-04-11 2000-05-23 Micron Technology, Inc. Honeycomb capacitor and method of fabrication
US5869399A (en) * 1997-08-07 1999-02-09 Mosel Vitelic Inc. Method for increasing utilizable surface of rugged polysilicon layer in semiconductor device
CN1214542A (zh) * 1997-09-30 1999-04-21 西门子公司 集成电路制造方法及结构
JP2001185698A (ja) * 1999-12-24 2001-07-06 Fujitsu Ltd 半導体装置及びその製造方法
CA2411276C (en) 2000-06-15 2009-08-18 Reinz-Dichtungs-Gmbh & Co. Kg Flat gasket and method for the production thereof
AUPR174800A0 (en) 2000-11-29 2000-12-21 Australian National University, The Semiconductor processing
WO2003047004A1 (en) * 2001-11-29 2003-06-05 Origin Energy Solar Pty Ltd Semiconductor texturing process
US6544282B1 (en) * 2001-02-21 2003-04-08 Radiant Medical, Inc. Inhibition of platelet activation, aggregation and/or adhesion by hypothermia
US6972473B2 (en) * 2003-08-12 2005-12-06 Tessera, Inc. Structure and method of making an enhanced surface area capacitor
EP3009028A1 (en) 2014-10-13 2016-04-20 Sven Dobler Dry peel cosmetic sampler
US9391069B1 (en) 2015-12-03 2016-07-12 International Business Machines Corporation MIM capacitor with enhanced capacitance formed by selective epitaxy

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123687A (en) * 1977-04-04 1978-10-28 Nec Corp Binary memory element
CA1148895A (en) * 1980-02-06 1983-06-28 Dan Maydan Reactive sputter etching of silicon
US5136533A (en) * 1988-07-08 1992-08-04 Eliyahou Harari Sidewall capacitor DRAM cell
US5043780A (en) * 1990-01-03 1991-08-27 Micron Technology, Inc. DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100427540B1 (ko) * 1997-06-25 2004-07-19 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100260486B1 (ko) * 1997-06-30 2000-08-01 김영환 반도체장치의전하저장전극형성방법

Also Published As

Publication number Publication date
US5149676A (en) 1992-09-22
KR930008580B1 (ko) 1993-09-09
US5304828A (en) 1994-04-19
JP2519612B2 (ja) 1996-07-31
JPH0621336A (ja) 1994-01-28

Similar Documents

Publication Publication Date Title
KR920001625A (ko) 표면적이 극대화된 실리콘층 및 그 제조방법
US4690728A (en) Pattern delineation of vertical load resistor
KR960043106A (ko) 반도체장치의 절연막 형성방법
JP2001035841A (ja) ペロブスカイト強誘電性材料のウェット・エッチング・プロセスと溶液
KR930015002A (ko) 반도체 메모리 장치 및 그 제조방법
KR100265340B1 (ko) 반도체소자 제조방법
KR100187654B1 (ko) 반도체 소자의 제조방법
KR950021130A (ko) 반도체 소자의 콘택홀 제조방법
KR950021090A (ko) 반도체 소자의 콘택홀 형성방법
KR0169759B1 (ko) 반도체 소자의 텅스텐 플러그 형성 방법
KR100252769B1 (ko) 반도체소자의전도층형성방법
KR960002742A (ko) 반도체소자의 제조방법
JPS583252A (ja) 半導体集積回路装置
KR100585955B1 (ko) 반도체 장치의 제조 방법
KR960002578A (ko) 반도체소자의 전하보존전극 제조방법
KR930003366A (ko) 반도체 장치의 소자 분리방법
KR950021371A (ko) 반도체 소자의 소자분리산화막 제조방법
KR960001880A (ko) 반도체소자의 실리콘층 제조방법
KR960026400A (ko) 반도체소자의 다결정실리콘 배선 제조방법
KR960026475A (ko) 반도체 소자의 게이트전극 형성방법
KR940022854A (ko) 반도체장치의 접촉창 형성방법
KR940001435A (ko) 반도체소자의 격리방법
KR950004539A (ko) 반도체 기억장치 및 그 제조방법
KR960039420A (ko) 3극 필드 에미터 제조방법
KR960002789A (ko) 반도체소자의 캐패시터 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090828

Year of fee payment: 17

EXPY Expiration of term