EP1522103A1 - Feldeffekttransistor, zugehörige verwendung und zugehöriges herstellungsverfahren - Google Patents
Feldeffekttransistor, zugehörige verwendung und zugehöriges herstellungsverfahrenInfo
- Publication number
- EP1522103A1 EP1522103A1 EP03787593A EP03787593A EP1522103A1 EP 1522103 A1 EP1522103 A1 EP 1522103A1 EP 03787593 A EP03787593 A EP 03787593A EP 03787593 A EP03787593 A EP 03787593A EP 1522103 A1 EP1522103 A1 EP 1522103A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- effect transistor
- field effect
- recess
- connection
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 59
- 230000015654 memory Effects 0.000 claims description 35
- 238000009413 insulation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000010292 electrical insulation Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000012876 carrier material Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000011161 development Methods 0.000 description 14
- 230000018109 developmental process Effects 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 14
- 239000000758 substrate Substances 0.000 description 14
- 238000002955 isolation Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000001459 lithography Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000543 intermediate Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the invention relates to a field effect transistor which contains a doped channel region, two connection regions, which are also referred to as drain or source, a control region, which is also referred to as gate, and an electrical insulation region between the control region and the channel region in a semiconductor layer.
- the semiconductor layer is made of a material that has a specific electrical resistance between 10 ⁇ 4 ⁇ / cm to 10 8 ⁇ / cm (ohms per centimeter), for example silicon or gallium arsenide.
- the semiconductor layer is, for example, a semiconductor substrate with an n-doping or p-doping.
- SOI technology Silicon on Insulator
- the field effect transistors are differentiated into n-channel transistors and p-channel transistors depending on the type of channel that is formed in the channel area.
- a large number of field effect transistors are arranged in an integrated circuit arrangement, so that even small improvements or changes in the structure of a field effect transistor can lead to considerable improvements and increases in yield.
- the field effect transistor according to the invention contains a recess in the semiconductor layer, in which the control region and the electrical insulation region are arranged.
- the channel region runs in the semiconductor layer along the depression.
- the depression has an opening in a surface of the semiconductor layer to be processed, in the vicinity of which there is a connection region.
- the other connection area is further away from the opening than the connection area near the opening and is therefore referred to as the connection area remote from the opening.
- the connection area remote from the opening lies, for example, at the end of the depression.
- the opening is remote
- the field effect transistor according to the invention is thus a field effect transistor whose channel region extends in the vertical direction to the surface of the semiconductor layer or at least transversely to this surface.
- the area required for the field effect transistor is independent of the required channel length or only dependent on the channel area by a factor of less than one.
- the integration of the transistor in an integrated electrical circuit is not more complex because of the inside of the
- Semiconductor layer lying remote from the opening leads to the surface to be processed or with this upper surface is electrically conductively connected via an electrically conductive connection.
- the two connection regions have the same dopant concentration and dopants of the same conductivity type, i.e. either n-type or p-type.
- the channel area has a doping of the opposite conductivity type as the connection areas and borders on both connection areas. Additional doping regions between the connection regions are not present in this embodiment.
- the channel area has a length that corresponds to at least two thirds of the depth of the depression.
- the deepening is only made as deep as is necessary to achieve the required channel length.
- the depression is a trench.
- the length of the trench determines the transistor width, i.e. a relevant parameter of the field effect transistor.
- the depression is a hole that has a depth that exceeds the diameter or the width of the hole, for example, by at least twice.
- the diameter of the hole determines the transistor width.
- the depth determines the gate length.
- layers can be deposited very uniformly on the hole wall.
- ⁇ of the channel region is located on both sides of the trench or along the entire circumference of the hole.
- transistors can provide a relatively large transistor width easily ago ⁇ .
- the channel region lies only on one side of the trench or only along part of the circumference of the hole. Transistors that only need a comparatively small width can thus be manufactured in a simple manner.
- the areas on the trench or on the circumference of the hole which are not occupied by the channel area are used for arranging other components or as part of isolation areas.
- connection area remote from the opening extends in the area of a plurality of depressions in which control areas are arranged.
- the field effect transistor contains two, three or more wells, which are arranged in the manner of a cascade. Cascading leads to a further reduction in space requirements.
- the connection area remote from the opening per field effect transistor only has to be brought to the surface once.
- the depression for the control area and a depression filled with an electrical insulating material between the field effect transistor and an adjacent electronic component have the same depth. Both recesses can thus be produced in a simple way in a common lithography process.
- the recess for the control region has a smaller depth than a completely filled with an electrical insulating material Ver ⁇ deepening between the field effect transistor and an adjacent electronic device. This measure allows the groove for the insulating narrowgonal ⁇ ren without compromising insulation compared to a wider insulation, however, is not so deep.
- the individual elements of the field effect transistor have dimensions and / or a structure which allow the switching of voltages greater than 9 volts, greater than 15 volts, but less than 30 volts:
- the insulation region has, for example, an insulation thickness of at least 15 nm (nanometers ) or at least 20 nm, the distance between the connection areas along the recess is at least 0.4 ⁇ m (micrometer), - the connection areas have a flat doping profile gradient of approximately 200 nm / decade compared to the doping profiles of planar field effect transistors.
- the flat doping profile gradient can be generated in a simple manner due to the different penetration depths of the dopants.
- the aforementioned measures can be used to produce field effect transistors which, in comparison to planar field effect transistors with the same electrical properties, require only less than half the area required.
- the saving of space is particularly large in the range of the switching voltages mentioned and clearly outweighs the manufacturing outlay for producing the depression.
- the invention also relates to the use of the field effect transistor, in particular the field effect transistor for the switching voltages mentioned, as a control transistor on a word line or a bit line of a memory cell array.
- the switching voltages mentioned are required in particular for erasing, but also for programming non-volatile memory cells, such as so-called flash memories in which only several cells can be erased at the same time, or EEPROMs (Electrical Erasable Programmable Read Only Memory) ,
- the field effect transistors according to the invention are used with a degree of integration of the memory cell field in which the memory cell field would take up less than 30 percent of the chip area of a memory unit when using planar field effect transistors for the control.
- the invention also relates to a particularly simple production method for producing the field effect transistor according to the invention, in which: a semiconductor layer with a surface to be processed is provided, a connection region close to the surface and a connection region remote from the surface are doped into the semiconductor layer, at least one depression for a control region is etched from the connection area close to the surface to the connection area remote from the surface, an electrical insulating layer is deposited in the depression, and an electrically conductive control area is introduced into the depression.
- the doping of the connection regions is carried out before the etching and the
- connection area is doped which leads from the connection area remote from the surface to the surface.
- the doping creates an electrically conductive connection in the semiconductor layer in a simple manner.
- isolation depressions so-called isolation trenches
- the isolation wells have the same depth as the depression for the control area.
- the isolation wells are deeper than the control area well.
- an additional lithography process is carried out in addition to the lithography process for producing the recess for the control area.
- the isolation recesses are etched either to their entire depth or to the depth that they exceed the depth of the recess for the control area.
- the depressions are etched using a common etching process in which wider depressions are etched considerably deeper than narrower depressions.
- FIG. 3 shows the use of vertical field effect transistors for driving a memory cell array in an EEPROM
- FIG. 4 shows a plan view of a vertical field effect transistor
- FIG. 5 shows a section through a vertical field effect transistor with double cascaded gate
- FIG. 6 shows a plan view of vertical field effect transistors connected in parallel with cylindrical gate regions.
- a process sequence is explained below with which vertical transistors for switching voltages between 9 volts and 20 volts can be produced with any cascading of gate regions. Many process steps of the process sequence can be combined with process steps for producing other components of the same integrated circuit arrangement and carried out together, e.g. with process steps for the production of shallow trench isolation (STI - Shallow Trench Isolation) or of gate stacks of planar field effect transistors.
- STI shallow trench isolation
- Two process variants are explained, of which the first process variant relates to vertical field effect transistors with trenches of the same depth and is explained using FIGS. 1A to 1J:
- FIG. 1A shows a p-doped semiconductor substrate 10.
- an oxide layer 12 made of silicon dioxide is produced, which for example has a thickness of 5 nm and was produced at 800 ° C. by dry oxidation for an oxidation period of about ten minutes.
- a nitride layer 14 is then deposited, for example made of silicon nitride.
- the nitride layer 14 has a thickness of 100 nm, for example, and was produced, for example, using an LPCVD (Low Pressure Chemical Vapor Deposition) process. Subsequently, optional flat ones
- Isolation trenches are produced in other areas of the silicon substrate 10.
- a photoresist layer is then applied, exposed and developed on the nitride layer 14, a recess being created over the later drain region 16.
- An ion implantation is then carried out, in which the drain region 16 is heavily n-doped, ie receives an n + - doping. The remnants of the photoresist layer are then removed.
- a next lithography process for generating a source region 18 is then carried out.
- a photoresist layer 20 is applied to the nitride layer 14.
- the photoresist layer 20 is exposed and developed, a recess 22 being formed through which ions penetrate into the source region 18 to be doped during a subsequent ion implantation, see arrows 24.
- the drain region 16 and the source region 18 can also be produced with the same photomask if they are to have the same lateral dimensions.
- the distance from the surface of the semiconductor substrate 10 and thus from the top of the drain region 16 and the center of the source region 18 is 1 ⁇ m in the exemplary embodiment.
- a concentration of approximately 10 20 cm -3 (doping atoms per cubic centimeter) is selected, for example, as the dopant concentration in the drain region 16 and in the source region 18.
- a photoresist layer 50 is applied to the nitride layer 14.
- the photoresist layer 50 is exposed and developed, so that a cutout 52 is formed above the edge regions of the drain region 16 or the source region 18.
- ions penetrate in several successive implantation steps with decreasing implantation depths vertical connection region 54 n - doping.
- the connection region 54 initially connects the drain region 16 and the source region 18. After the ion implantation represented by the arrows 56, the remnants of the photoresist layer 50 are removed.
- the implantation steps can also be carried out at later times if this is more appropriate in the context of the overall process management, e.g. after the etching of trenches to produce the field effect transistor.
- a hard mask layer 60 is then applied to the nitride layer 14.
- the hard mask layer 60 consists, for example, of TEOS (tetraethyl orthosilicate).
- TEOS tetraethyl orthosilicate
- a photoresist layer is deposited on the hard mask layer 60, exposed and structured.
- the hard mask 60 is then opened in areas 62, 64, 66 and 68 above trenches to be produced in an etching process.
- the hard mask 60 is then used to produce trenches 70, 72, 74 and 76, which are lined up in this order along the drain region 16 and along the source region 18.
- the trenches 70, 72 and 74 have a width B1 of, for example, 150 nm and a depth of, for example, 1 ⁇ m.
- the trench 76 has a width B2, which in the exemplary embodiment is approximately twice as large as the width B1.
- the trench 76 is also approximately 1 ⁇ m deep in the exemplary embodiment. All trenches 70 to 76 extend to the source region 18 and end approximately in the middle of the source region 18.
- the trench 74 separates the drain region 16 from the connection region 54.
- the trenches 70 to 76 are at their bottom more rounded than shown in the figures IC.
- the remains of the hard mask 60 are then removed.
- the residues of the nidrid layer 14 can then optionally be removed. In the exemplary embodiment, the remains of However, nitride layer 14 is not removed. As shown in FIG. 1D, an oxidation is then carried out to produce a thin sacrificial oxide layer 100 which is 10 nm thick, for example. The oxidation is carried out, for example, at a temperature of 800 ° C.
- a sacrificial nitride layer 102 is then applied to the sacrificial oxide layer 100, which is, for example, 6 nm thick and is produced using an LPCVD process (Low Pressure Chemical Vapor Deposition).
- a bottom oxide 120, 122, 124 or 126 is optionally introduced into the trenches 70 to 76, e.g. in an HDP process (High Density Plasma).
- the oxide deposited using the HDP method is etched back using an etch-back process until only the bottom oxide 120, 122, 124 or 126 remains on the bottom of the trenches 70 to 76.
- the trenches 70 to 76 are then undoped
- Sacrificial polysilicon 130 padded.
- the sacrificial polysilicon 130 is then removed in a planarization step up to the upper edge of the trenches 70 to 76, e.g. with the help of a chemical-mechanical polishing process.
- a photoresist layer 140 is applied, exposed and developed on the planarized surface in a subsequent method step, with recesses 142, 144 and 146 being formed above the trench 70, 74 and 76, respectively.
- the photoresist layer 140 is closed above the trench 72.
- the sacrificial polysilicon 130 arranged in the trenches 70, 74 and 76 is then wet-chemically selectively etched to the sacrificial nitride layer 102. Bottom oxide 120, 124 and 126, respectively, remain in trenches 70, 74 and 76. Residues of photoresist layer 140 are then removed.
- the sacrificial nitride layer 102 on the walls of the trenches 70, 74 and 76 can be removed in a subsequent etching step.
- this is not absolutely necessary because the sacrificial nitride layer 102 can also remain in the trenches 70, 74 and 76.
- insulation material 150 is then deposited in trenches 70, 74 and 76, e.g. TEOS.
- the insulation material 150 also extends over the edge of the trenches 70, 74 and 76, so that it fills the trenches 70, 74 and 76 and at the same time acts as an insulation layer in other parts of the transistor.
- a photoresist layer 160 is then applied, exposed and developed, so that a cutout 162 is formed above the trench 72 in which a gate region is to be formed.
- the insulation layer 150 in the region of the cutout 162 is then removed.
- sacrificial polysilicon 130 is removed from trench 72, e.g. using a wet chemical etching process selectively to the sacrificial nitride layer 102 within the trench 72.
- the bottom oxide 122 remains in the trench 72.
- the residues of the photoresist layer 160 are then removed.
- the sacrificial nitride layer 102 and the sacrificial oxide layer 100 within the trench 72 are then removed using two etching processes.
- the trench 72 is thus free for the deposition of a gate oxide in a subsequent process step.
- the bottom oxide 122 remains on the bottom of the trench 72, which promotes the clean deposition of the gate oxide in the region of the corners of the trench 72 and in the region of the lower edges of the trench 72.
- a gate oxide layer 170 is deposited on the sidewalls of the trench 72 using thermal oxidation.
- the gate oxide layer 170 consists of for example made of silicon dioxide and has, for example, a thickness of 20 nm.
- the oxidation for producing the gate oxide layer 170 is carried out, for example, in a temperature range from 800 ° C. to 1000 ° C.
- amorphous silicon 172 is deposited in the trench 72, which is, for example, n-doped and thus electrically conductive.
- the trench 72 is filled conformally, for example, using an LPCVD method, so that no holes or voids are created within the trench 72.
- a chemical mechanical polishing process is performed, which stops on the insulating material 150.
- An oxide cap is then optionally produced above the trench 72 at, for example, a temperature of 900 ° C. and an oxidation time of, for example, ten minutes in a wet oxidation process.
- contact holes are etched, which lead to the drain region 16, to the connection region 54 or to the gate region formed by the amorphous silicon 172.
- the known method steps for producing transistors are then carried out.
- MOS transistor Metal Oxide Semiconductor
- the gate length is equal to the distance from the source region 16 to the drain region 18, that is to say approximately the depth of the trench.
- the gate width is equal to the length of the trench 72, which is not shown in the cross-sectional images.
- a p-channel field effect transistor is basically produced in the same way as explained with reference to FIGS. 1A to IJ. However, an n-doped silicon substrate 10 or a correspondingly doped trough is assumed. The dopings generated with reference to FIGS. 1A to IJ are carried out with doping material of the opposite conductivity type.
- a trench 76a corresponding to the trench 76 is produced with the trench width Bl, ie four trenches 70a to 76a have the same width Bl and the same depth.
- FIG. 2A the same elements as in FIGS. 1A to 1B are denoted by the same reference numerals, but with a lower case letter a.
- the trenches 70a to 76a thus run through recessed areas 62a to 68a of a hard mask layer 60a.
- the hard mask layer 60a was applied to a nitride layer 14a, which in turn lies on a thin oxide layer 12a.
- All trenches 70a to 76a lie in a silicon substrate 10a.
- a drain region 16a which corresponds to the drain region 16, lies immediately below the oxide layer 12a.
- the trenches 62a to 68a extend into a "buried" source region 18a.
- the trenches 70a to 76a are then filled with a filler material 200 which can be easily removed selectively against silicon, for example a photoresist, polycrystalline germanium or polycrystalline silicon germanium.
- the filler material 200 is subsequently removed from the trenches 70a and 76a again using an etching step after a lithography process has been carried out.
- An additional etching is then carried out, in which the trenches 70a and 76a are deepened, so that their bottom 202 and 204 is clearly below the source region 18a.
- p-field effect transistors can also be produced.
- the length of the gate region is likewise essentially determined by the depth of the trench 72a.
- the insulation to the adjacent component has only a width B1 of the deep trench 76a, for example only around 100 to 200 nm.
- FIG. 3 shows the use of vertical field effect transistors 220 to 226 of a memory cell array 230.
- the vertical field effect transistors 220 to 226 are part of a control unit 232 which is separated from the memory cell array 230 in FIG. 3 by a broken line 234.
- the control unit 232 controls the memory cell array 230, for example according to the so-called NOR method or according to the NAND method.
- the vertical transistors 220 to 226 were manufactured using a method as was explained above with reference to FIGS. 1A to IJ or 2A and 2B.
- Connections 240, 242, 244 and 246 of transistors 220, 222, 224 and 226 are in this order at potentials of 10 volts, 16 volts, -10 volts and +10 volts.
- Gate connections 250 to 256 of transistors 220 to 226 are controlled by a control unit (not shown) in order to control memory cells of memory cell array 230 in accordance with a programming method or erasure method. However
- FIG. 3 shows a basic circuit for a memory cell 260 of the memory cell array 230. Additional memory cells of a memory matrix are indicated by arrows 262. The other memory cells of the memory cell array 230 are constructed like the memory cell 260.
- the memory cell 260 contains a memory transistor 264 and a drive transistor 266.
- the memory transistor 264 is a field effect transistor with a charge-storing intermediate layer 268 between a gate connection 270 and a channel region.
- the gate terminal 270 is connected to a word line 272, which leads to a terminal 274 of the transistor 224 and to a terminal 276 of the transistor 226.
- a connection 278 of the transistor 264 leads to an auxiliary line 280, the potential of which for programming and erasing the memory cell 260 has no influence.
- a terminal 282 of transistor 264 is connected to a terminal 284 of transistor 266.
- a gate connection 286 of the transistor 266 leads to a further word line 288, which is connected to a connection 290 of the transistor 220 and to a connection 292 of the transistor 222.
- a connection 294 of the transistor 266 is connected to a bit line 296, to which the control unit 232 connects Program a voltage of 6 volts and when erasing memory cell 260 a voltage of 0 volts is applied.
- the memory cells explained with reference to FIG. 3 are memory cells of an EEPROM.
- flash memory modules there is only one memory transistor in a memory cell 260.
- a drive transistor 266 is not required.
- memory transistor 264 and drive transistor 266 are implemented in one transistor, i.e. in a so-called split gate transistor.
- FIG. 4 shows a plan view of the vertical field effect transistor 222, which was produced in accordance with the first process variant.
- a rectangle 300 circumscribes the chip area required for transistor 222, including one
- An insulation distance AI in the longitudinal direction of the rectangle 300 has the width Bl of the trench 76.
- An insulation distance A2 in the transverse direction of the rectangle 300 also has the width Bl.
- a trench length L 1 is also shown in FIG. Since the walls on both sides of the trench 72 contribute to the transistor width, the electrically effective width W is twice as long as the trench length L1.
- FIG. 4 also shows source contacts 310 to 314, which lead to the buried source region 18 via the connection region 54.
- Two drain contacts 324 and 326 to the right of the trench 72 lead to the drain region between the trench 72 and the trench 74.
- the substrate contacts 340 and 342 are isolated from the drain region 16. By using the substrate contacts 340 and 342, separate n, p and so-called triple wells, as are common today, can be omitted.
- the drain region is at the end of the trenches 70 to 76 and the source region is in the vicinity of the substrate surface.
- FIG. 5 shows a cross section through a vertical field effect transistor 350 with double cascaded gate regions.
- the field effect transistor 350 When producing the field effect transistor 350, four trenches 70b, 72b, 74b and 76b are produced which correspond to the trenches 70 to 76 and the trenches 70a to 76a. However, an additional trench 352, which has the same dimensions and the same fillings as the trench 72b, was produced between the trench 72b and the trench 74b.
- the distance between the trenches 72b and 74b in the transistor 350 is approximately twice as large as the distance between the trenches 72 and 74 or between the trenches 72a and 74a in order to make room for the trench 352.
- the channel is formed along vertical side walls 360 to 366 of the trench 72b or the trench 352. Arrows 370 to 376 indicate four times the current flow from drain regions 16c to a source region 18c.
- the control areas in the trenches 72b and 352 are electrically connected in parallel, see connections 380.
- the drain regions 16c are also connected electrically in parallel, see connections 382.
- the channel length 1 of a channel is represented by an arrow in FIG.
- control areas or more than four channel areas are cascaded in one transistor.
- transistors with a minimal width W are also used in the control units for controlling a memory cell array.
- the highly doped connection region 54, 54a or 54b can directly connect to the trench 72b for the control area.
- the channel is only formed on a trench wall, e.g. on the wall 360 of the trench 72b.
- FIG. 6 shows a plan view of three vertical field effect transistors 400, 402 and 404 connected in parallel, which have cylindrical depressions for the control regions instead of the trenches.
- cylindrical depressions are particularly suitable for very wide transistors, because the reduction in layout width is particularly high with cylindrical depressions.
- U 2 Pi r, where U is the circumference or width, Pi is the number of the same name and r is the radius of the cylindrical recess.
- the channel region is completely insulated from the substrate, namely laterally through the trenches and in depth through the buried source or drain region. Because of this arrangement, a resembles such a transistor in a way a SOI transistor (Silicon On Insulator).
- SOI transistor Silicon On Insulator
- punch strength of SOI transistors is significantly better than that of bulk transistors. This advantage is also transferred to the vertical field effect transistors. This can reduce the depth of the vertical transistors.
- the so-called driver capability of the vertical field-effect transistor is increased by adopting properties of an SOI transistor.
- the transistor width can thereby be reduced while the electrical properties remain the same.
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- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Non-Volatile Memory (AREA)
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Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10231966A DE10231966A1 (de) | 2002-07-15 | 2002-07-15 | Feldeffekttransistor, zugehörige Verwendung und zugehöriges Herstellungsverfahren |
DE10231966 | 2002-07-15 | ||
PCT/DE2003/001957 WO2004017417A1 (de) | 2002-07-15 | 2003-06-12 | Feldeffekttransistor, zugehörige verwendung und zugehöriges herstellungsverfahren |
Publications (1)
Publication Number | Publication Date |
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EP1522103A1 true EP1522103A1 (de) | 2005-04-13 |
Family
ID=30128124
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03787593A Ceased EP1522103A1 (de) | 2002-07-15 | 2003-06-12 | Feldeffekttransistor, zugehörige verwendung und zugehöriges herstellungsverfahren |
Country Status (8)
Country | Link |
---|---|
US (2) | US7786530B2 (de) |
EP (1) | EP1522103A1 (de) |
JP (2) | JP4926401B2 (de) |
KR (1) | KR20050021469A (de) |
CN (1) | CN100409455C (de) |
DE (1) | DE10231966A1 (de) |
TW (1) | TWI270210B (de) |
WO (1) | WO2004017417A1 (de) |
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US7600118B2 (en) | 2002-09-27 | 2009-10-06 | Intel Corporation | Method and apparatus for augmenting authentication in a cryptographic system |
US7279397B2 (en) * | 2004-07-27 | 2007-10-09 | Texas Instruments Incorporated | Shallow trench isolation method |
JP4414863B2 (ja) | 2004-10-29 | 2010-02-10 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
US7816728B2 (en) * | 2005-04-12 | 2010-10-19 | International Business Machines Corporation | Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications |
KR100680977B1 (ko) * | 2006-02-17 | 2007-02-09 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
JP5466818B2 (ja) * | 2007-09-27 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
JP5602414B2 (ja) * | 2009-11-05 | 2014-10-08 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法および半導体装置 |
JP2012094762A (ja) * | 2010-10-28 | 2012-05-17 | Elpida Memory Inc | 半導体装置および半導体装置の製造方法 |
US9828696B2 (en) | 2011-03-23 | 2017-11-28 | Nanohmics, Inc. | Method for assembly of analyte filter arrays using biomolecules |
US8476704B2 (en) * | 2011-08-19 | 2013-07-02 | Nan Ya Technology Corporation | Circuit structure with vertical double gate |
US10386351B2 (en) | 2015-12-07 | 2019-08-20 | Nanohmics, Inc. | Methods for detecting and quantifying analytes using gas species diffusion |
US11988662B2 (en) | 2015-12-07 | 2024-05-21 | Nanohmics, Inc. | Methods for detecting and quantifying gas species analytes using differential gas species diffusion |
US10386365B2 (en) | 2015-12-07 | 2019-08-20 | Nanohmics, Inc. | Methods for detecting and quantifying analytes using ionic species diffusion |
US9882048B2 (en) | 2016-06-30 | 2018-01-30 | International Business Machines Corporation | Gate cut on a vertical field effect transistor with a defined-width inorganic mask |
DE102017101662B4 (de) | 2017-01-27 | 2019-03-28 | Infineon Technologies Austria Ag | Halbleiterbauelement mit einer Isolationsstruktur und einer Verbindungsstruktur sowie ein Verfahren zu dessen Herstellung |
US10468485B2 (en) * | 2017-05-26 | 2019-11-05 | Allegro Microsystems, Llc | Metal-oxide semiconductor (MOS) device structure based on a poly-filled trench isolation region |
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JP2950558B2 (ja) * | 1989-11-01 | 1999-09-20 | 株式会社東芝 | 半導体装置 |
JPH03154379A (ja) * | 1989-11-11 | 1991-07-02 | Takehide Shirato | 半導体装置 |
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2002
- 2002-07-15 DE DE10231966A patent/DE10231966A1/de not_active Withdrawn
-
2003
- 2003-05-27 TW TW092114319A patent/TWI270210B/zh not_active IP Right Cessation
- 2003-06-12 JP JP2004528310A patent/JP4926401B2/ja not_active Expired - Fee Related
- 2003-06-12 KR KR10-2005-7000624A patent/KR20050021469A/ko not_active Application Discontinuation
- 2003-06-12 WO PCT/DE2003/001957 patent/WO2004017417A1/de active Application Filing
- 2003-06-12 US US10/521,528 patent/US7786530B2/en not_active Expired - Fee Related
- 2003-06-12 CN CNB038167794A patent/CN100409455C/zh not_active Expired - Fee Related
- 2003-06-12 EP EP03787593A patent/EP1522103A1/de not_active Ceased
-
2010
- 2010-02-11 US US12/704,287 patent/US7989294B2/en not_active Expired - Fee Related
-
2011
- 2011-12-27 JP JP2011286372A patent/JP2012109588A/ja active Pending
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Also Published As
Publication number | Publication date |
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US20100142266A1 (en) | 2010-06-10 |
TW200402883A (en) | 2004-02-16 |
US20060211264A1 (en) | 2006-09-21 |
CN1669152A (zh) | 2005-09-14 |
TWI270210B (en) | 2007-01-01 |
US7786530B2 (en) | 2010-08-31 |
CN100409455C (zh) | 2008-08-06 |
JP4926401B2 (ja) | 2012-05-09 |
DE10231966A1 (de) | 2004-02-12 |
JP2005538537A (ja) | 2005-12-15 |
KR20050021469A (ko) | 2005-03-07 |
JP2012109588A (ja) | 2012-06-07 |
US7989294B2 (en) | 2011-08-02 |
WO2004017417A1 (de) | 2004-02-26 |
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