EP0996962B1 - Resin molded type semiconductor device - Google Patents

Resin molded type semiconductor device Download PDF

Info

Publication number
EP0996962B1
EP0996962B1 EP98923185A EP98923185A EP0996962B1 EP 0996962 B1 EP0996962 B1 EP 0996962B1 EP 98923185 A EP98923185 A EP 98923185A EP 98923185 A EP98923185 A EP 98923185A EP 0996962 B1 EP0996962 B1 EP 0996962B1
Authority
EP
European Patent Office
Prior art keywords
portions
sealing resin
semiconductor chip
thin metal
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP98923185A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0996962A2 (en
Inventor
Masanori Minamio
Satoru Konishi
Yoshihiko Morishita
Yuichiro Yamada
Fumito Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26414858&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0996962(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of EP0996962A2 publication Critical patent/EP0996962A2/en
Application granted granted Critical
Publication of EP0996962B1 publication Critical patent/EP0996962B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a resin molded type semiconductor device in which a semiconductor chip is mounted on a lead frame and the outer periphery of the semiconductor chip, particularly, the upper face of the semiconductor chip is molded by a sealing resin, and also to a method of manufacturing the semiconductor device.
  • FIG. 5 is a section view showing a resin molded type semiconductor device of the prior art.
  • a semiconductor chip 3 is mounted on a die pad portion 2 of a lead frame 1, and terminals (not shown) of the semiconductor chip 3 are electrically connected to inner lead portions 4 of the lead frame 1 by thin metal wires 5.
  • the outer peripheral region of the semiconductor chip 3 is molded by a sealing resin 6.
  • a resin molded type semiconductor device produced so as to have a structure such as shown in Fig. 5 is provided with a structure in which an outer lead portion 7 serving as external terminals is arranged on a bottom face of the semiconductor device. Since only the face of the lead frame 1 on which the semiconductor chip 3 is mounted is molded by the sealing resin 6 and the rear face of the lead frame 1 is not substantially molded, it is possible to realize a thin resin molded type semiconductor device.
  • a tapered shape is first formed at tip end portions of the inner lead portions 4 of the lead frame 1 by mechanical or chemical working, and the semiconductor chip 3 is then bonded onto the lead frame 1. Thereafter, the semiconductor chip 3 is electrically connected to the inner lead portions 4 of the lead frame 1 by the thin metal wires 5, and the face of the lead frame 1 for mounting the semiconductor chip 3 is then molded by the sealing resin 6 by means of transfer molding. In order to form external terminals, finally, the outer lead portion 7 of the lead frame 1 which projects from the sealing resin 6 is worked, thereby completing the resin molded type semiconductor device.
  • an insulative resin tape 8 on which a semiconductor chip 3 is to be mounted is bonded to tip end portions 4a of inner lead portions 4 of a lead frame 1, thereby forming a die pad portion.
  • the device has a structure in which, after the semiconductor chip 3 is mounted on the resin tape 8, terminals of the semiconductor chip 3 are electrically connected to the inner lead portions 4 by thin metal wires 5, and the face of the lead frame 1 for mounting the semiconductor chip 3 is molded by a sealing resin 6.
  • the resin molded type semiconductor device shown in Fig. 6 has the merit that the device can be made thinner than the resin molded type semiconductor device shown in Fig. 5 . Specifically, in the resin molded type semiconductor device shown in Fig.
  • the resin tape 8 is bonded to the lower faces of the inner lead portions 4 of the lead frame 1 and the semiconductor chip 3 is mounted on the upper face of the portion. Therefore, the step difference between the upper faces of the inner lead portions 4 and the upper face of the semiconductor chip 3 is reduced. As a result, also the resin thickness of the sealing resin 6 is reduced, and the resulting resin molded type semiconductor device has a reduced thickness.
  • the thickness of the sealing resin 6 cannot be reduced by such a degree that is attained in the resin molded type semiconductor device shown in Fig. 6 .
  • a resin molded type semiconductor device of the prior art has a structure in which substantially only the face of a lead frame on which a semiconductor chip is mounted, i.e. , the upper face of the lead frame is molded by a sealing resin. Even when a tapered shape is formed in an inner lead portion, therefore, the contact area between the lead frame and the sealing resin is reduced as a whole, thereby producing a problem in that the adhesiveness is impaired and the reliability of a product is lowered. Since such a device has a structure in which substantially only the single face of the lead frame is resin-molded, there are further problems in that the semiconductor chip is adversely affected by stress of the sealing resin, and that package crack occurs in the sealing
  • Document EP 0 628 997 A2 discloses a semiconductor device package having a lead frame with a mounting pad smaller than the IC chip mounted thereon. Separation between the mounting pad and an encapsulating resin is eliminated.
  • Document EP 0 628 997 A2 discloses a semiconductor device package having a lead frame with a mounting pad smaller than the IC chip mounted thereon. Separation between the mounting pad and an encapsulating resin is eliminated.
  • Document JP 61-001042 discloses a semiconductor chip which is die bonded to a bed of a lead frame, internal leads arranged around the bed connected with electrodes through metal wirings on the chip, and sealed by thermosetting resin. A recess is formed on the leads.
  • Recesses and projections may be alternately formed on both ends of the leads.
  • the above recess or projection is engaged with the resin at the inner leads to increase the contacting area.
  • Document JP 61-001042 discloses a semiconductor chip which is die bonded to a bed of a lead frame, internal leads arranged around the bed connected with electrodes through metal wirings on the chip, and sealed by thermosetting resin. A recess is formed on the leads. Recesses and projections may be alternately formed on both ends of the leads. The above recess or projection is engaged with the resin at the inner leads to increase the contacting area.
  • a resin molded type semiconductor device may comprise: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including a thin metal wire region of the upper face of the semiconductor chip, and a lower region of the die pad portion; and outer lead portions which are arranged in a bottom face region of the sealing resin, and is characterized in that the lead frame is subjected to an upsetting process so that the die pad portion is located at a position higher than the inner lead portions.
  • the lead frame is subjected to an upsetting process so that the die pad portion is located at a position higher than the inner lead portions. Therefore, the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the die pad portion, the adhesiveness between the lead frame and the sealing resin can be improved, and the reliability of a product can be maintained. Even when both the faces, or the upper and lower faces of the lead frame are resin-molded, the thickness of the resin of the lower face is equal to a value corresponding to the step difference of the upsetting. Consequently, the thinning can be realized.
  • a resin molded type semiconductor device may comprise: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including a thin metal wire region of the upper face of the semiconductor chip; and outer lead portions which are arranged in a bottom face region of the sealing resin and which are formed to be continuous to the respective inner lead portions, wherein at least one groove portion is formed in a surface of each of the inner lead portions.
  • At least one groove portion is formed in the surface of each of the inner lead portions. Therefore, the anchoring effect to the sealing resin can be improved, stress acting on a lead portion of a product, and stress to the thin metal wires can be relaxed, and leads and the thin metal wires can be prevented from peeling off. Consequently, the reliability of a product can be maintained.
  • the resin molded type semiconductor device of the invention comprises: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including the thin metal wires; and outer lead portions which are arranged in a bottom face region of the sealing resin and which are formed to be continuous to the respective inner lead portions, wherein a plurality of groove portions are formed in a surface of each of the inner lead portions, and a connecting portion of the thin metal wires on a side of the inner lead portion is disposed between the groove portions.
  • a plurality of groove portions are formed in the surface of each of the inner lead portions, and a connecting portion of the thin metal wire on the side of the inner lead portion is disposed between the groove portions. Therefore, the anchoring effect to the sealing resin can be improved, stress acting on a lead portion of a product, and stress to the thin metal wires can be relaxed, and leads and the thin metal wires can be prevented from peeling off. In this case, stress due to the structure in which the single face of the lead frame is molded by the sealing resin is absorbed by the groove portions, and does not act on an area between the groove portions. Therefore, the connecting portions of the thin metal wires are not broken and stable connection is enabled.
  • a resin molded type semiconductor device may comprise: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including a thin metal wire region of the upper face of the semiconductor chip; and outer lead portions which are arranged in a bottom face region of the sealing resin and which are formed to be continuous to the respective inner lead portions, and is characterized in that a widened portion is formed in each of the inner lead portions.
  • a resin molded type semiconductor device may comprise: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including a thin metal wire region of the upper face of the semiconductor chip; and outer lead portions which are arranged in a bottom face region of the sealing resin and which are formed to be continuous to the respective inner lead portions, and is characterized in that a widened portion is formed in each of the inner lead portions and at least one groove portion is formed in a surface.
  • a widened portion is formed in each of the inner lead portions and at least one groove portion is formed in the surface. Therefore, the anchoring effect to the sealing resin can be further improved, stress acting on a lead portion of a product, and stress to the thin metal wires can be further relaxed, and the effect of preventing leads and the thin metal wires from peeling off is enhanced.
  • a resin molded type semiconductor device may comprise: a semiconductor chip which is mounted on a die pad portion of a lead frame; thin metal wires which electrically connect terminals of an upper face of the semiconductor chip to inner lead portions of the lead frame; a sealing resin which seals an outer peripheral region of the semiconductor chip, the region including the thin metal wires; and outer lead portions which are arranged in a bottom face region of the sealing resin and which are formed to be continuous to each of the inner lead portions, and is characterized in that a widened portion is formed in each of the inner lead portions, a plurality of groove portions are formed in a surface, and connecting portions of the thin metal wires on a side of the inner lead portion are disposed between the groove portions.
  • a widened portion is formed in each of the inner lead portions, a plurality of groove portions are formed in the surface, and connecting portions of the thin metal wires on a side of the inner lead portion are disposed between the groove portions. Therefore, the anchoring effect to the sealing resin can be further improved, stress acting on a lead portion of a product, and stress to the thin metal wires can be further relaxed, and the effect of preventing leads and the thin metal wires from peeling off is enhanced. In this case, when two or more groove portions are disposed and the thin metal wires are connected to an area between the groove portions, the effect of absorbing stress can be enhanced.
  • exposed faces of the outer lead portions may be arranged in a same level as an outer face of the sealing resin.
  • the exposed faces of the outer lead portions are arranged in the same level as the outer face of the sealing resin.
  • the outer lead portions can be arranged so as to be embedded in the bottom face portion of the sealing resin, while the outer lead portions project from a side face of the sealing resin. Therefore, the reliability of the outer lead portions serving as external terminals can be improved, and it is possible to provide a resin molded type semiconductor device which is miniaturized by a size corresponding to the nonprojecting structure of the outer lead portions.
  • a method of manufacturing a resin molded type semiconductor device may comprise the steps of: performing an upsetting process on a lead frame so that a die pad portion is located at a position higher than inner lead portions; bonding a semiconductor chip to the die pad portion of the lead frame; electrically connecting terminals of the semiconductor chip to the inner lead portions of the lead frame by thin metal wires ; sealing an outer peripheral region of the semiconductor chip, thereby forming a sealing resin, the region including a region of an upper face of the semiconductor chip and electrically connected by the thin metal wires, and a lower region of the die pad portion; and shaping outer lead portions of the lead frame so as to be exposed from an outer face of the sealing resin.
  • the lead frame is subjected to an upsetting process so that the die pad portion is located at a position higher than the inner lead portions, and the outer peripheral region of the semiconductor chip including the region of the upper face of the semiconductor chip and electrically connected by the thin metal wires, and the lower region of the die pad portion is molded to form the sealing resin. Therefore, the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the die pad portion, the adhesiveness between the lead frame and the sealing resin can be improved, and the reliability of a product can be maintained. Even when both the faces, or the upper and lower faces of the lead frame are resin-molded, the thickness of the resin of the lower face is equal to the thickness of the step difference of the upsetting. Consequently, the thinning can be realized.
  • a method of manufacturing a resin molded type semiconductor device may comprise the steps of: bonding a semiconductor chip to a lead frame having inner lead portions in each of which a widened portion is disposed and at least one groove portion is formed in a surface; electrically connecting terminals of the semiconductor chip to the inner lead portions of the lead frame by thin metal wires; sealing an outer peripheral region of the semiconductor chip, thereby forming a sealing resin, the region including a region of an upper face of the semiconductor chip and electrically connected by the thin metal wires, and a lower region of the semiconductor chip; and shaping outer lead portions of the lead frame so as to be exposed from an outer face of the sealing resin, and, when the terminals of the semiconductor chip are to be electrically connected to the inner lead portions by the thin metal wires, the connection is performed while connecting portions of the thin metal wires on the side of the inner lead portions are disposed in the vicinity of the groove portion.
  • the connection is performed while connecting portions of the thin metal wires on the side of the inner lead portions are disposed in the vicinity of the groove portion. Therefore, stress due to the structure in which the single face of the lead frame is molded by the sealing resin is absorbed by the groove portion, the connecting portions of the thin metal wires are not broken, and stable connection is enabled. Moreover, the anchoring effect to the sealing resin can be improved, and stress acting on a lead portion of a product can be relaxed by the groove portion, and leads and the thin metal wires can be prevented from peeling off.
  • a method of manufacturing a resin molded type semiconductor device may comprise the steps of: bonding a semiconductor chip to a lead frame having inner lead portions in each of which a widened portion is disposed and a plurality of groove portions are formed in a surface; electrically connecting terminals of the semiconductor chip to the inner lead portions of the lead frame by thin metal wires; sealing an outer peripheral region of the semiconductor chip, thereby forming a sealing resin, the region including a region of an upper face of the semiconductor chip and electrically connected by the thin metal wires, and a lower region of the semiconductor chip; and shaping outer lead portions of the lead frame so as to be exposed from an outer face of the sealing resin, and, when the terminals of the semiconductor chip are to be electrically connected to the inner lead portions by the thin metal wires, the connection is performed while connecting portions of the thin metal wires on the side of the the side of the inner lead portions are disposed between the groove portions.
  • Fig. 1 is a section view showing a resin molded type semiconductor device of an embodiment of the invention
  • Fig. 2 is a plan view showing the resin molded type semiconductor device of the embodiment of the invention
  • Fig. 3 is an enlarged section view of main portions of the resin molded type semiconductor device of the embodiment of the invention
  • Fig. 4(a) is a plan view of an inner lead portion of the resin molded type semiconductor device of the embodiment of the invention
  • Fig. 4(b) is a left side view
  • Fig. 4(c) is a front view
  • Fig. 5 is a section view of a resin molded type semiconductor device of the prior art
  • Fig. 6 is a section view showing another example of a resin molded type semiconductor device of the prior art.
  • a resin molded type semiconductor device of an embodiment of the invention will be described with reference to Figs. 1 to 4 .
  • Fig. 1 is a section view of the resin molded type semiconductor device of the embodiment of the invention
  • Fig. 2 is a plan view of the device
  • Fig. 3 is an enlarged section view showing an inner lead portion of the device
  • Fig. 4(a) is an enlarged plan view showing a tip end of the inner lead portion
  • Fig. 4(b) is a left side view
  • Fig. 4(c) is a front view.
  • the plan view is a view which is obtained by partially removing away a sealing resin, in order to show the internal structure.
  • broken lines show a die pad portion and part of suspension leads.
  • the resin molded type semiconductor device comprises: a semiconductor chip 12 which is mounted on a die pad portion 11 of a lead frame 9 and serving as a supporting portion of the semiconductor chip 12 supported by suspension leads 10; thin metal wires 14 which electrically connect terminals of the upper face of the semiconductor chip 12 to inner lead portions 13 of the lead frame 9; a sealing resin 15 which seals an outer peripheral region of the semiconductor chip 12 including a thin metal wire 14 region of the upper face of the semiconductor chip 12, and a lower region of the die pad portion 11; and outer lead portions 16 which are arranged in a bottom face region of the sealing resin 15, which are formed to be continuous to the respective inner lead portions 13, and which serve as external terminals.
  • the lead frame 9 is subjected to an upsetting process so that the die pad portion 11 is located at a position higher than the inner lead portions 13.
  • the device is configured so that the die pad portion 11 is smaller in area than the semiconductor chip 12 to be mounted.
  • the suspension leads 10 are subjected to an upsetting process, and a step portion 17 is provided. Therefore, a sealing resin 15a can exist also below the die pad portion 11.
  • the device is of the thin type, the device is a semiconductor device which is substantially of the double-side molding type with respect to the lead frame 9.
  • each of the inner lead portions 13 has a widened portion 18 at a tip end portion, and a plurality of groove portions 19 are formed in the surface.
  • a reverse taper is formed in the thickness direction.
  • the outer lead portions 16 are arranged so that their exposed faces are in a substantially same level as a side face portion of the sealing resin 15, and do not protrude from the sealing resin 15 unlike the prior art configuration. Therefore, deformation of the outer lead portions 16, and the like can be prevented from occurring, and the device is a semiconductor device of the surface mount type.
  • the connecting portion of each thin metal wire 14 on the side of the inner lead portion 13 are disposed between the groove portions 19.
  • the resin molded type semiconductor device of the embodiment is a resin molded type semiconductor device which is very thin or has a total thickness of 0.7 [mm], and has a target thickness which is not larger than a sum of the thickness of a semiconductor chip and 1 [mm].
  • the step difference of the upsetting process of the suspension leads 10 is 0.1 [mm]
  • the thickness of the sealing resin 15a below the die pad portion 11 is 0.1 [mm].
  • the thickness of the semiconductor chip 12 is 0.2 [mm]
  • a sealing resin 15b above the die pad portion 11 is 0.15 [mm].
  • the suspension leads 10 supporting the die pad portion 11 of the lead frame 9 is pressurized to be subjected to an upsetting process, thereby forming the step portion 17.
  • the semiconductor chip 12 is bonded at the bottom face side to the die pad portion 11 of the lead frame 9 by an electrically conductive adhesive agent.
  • each thin metal wire 14 which is to be connected to the side of the corresponding inner lead portion 13 is connected so as to exist between two groove portions 19 which are disposed in the surface of the inner lead portion 13.
  • the outer peripheral region of the semiconductor chip 12 is molded by the sealing resin 15 by means of transfer molding.
  • the upper face of the semiconductor chip 12, i.e., the region where electrical connection is done by the thin metal wires 14, and the lower region of the die pad portion 11 are molded, thereby forming the sealing resin 15a and the sealing resin 15b.
  • the thickness of the sealing by the sealing resin 15 is set so that the sealing resin 15a below the die pad portion 11 is flush with the bottom face of the inner lead portion 13 and the sealing resin 15b on the upper face of the semiconductor chip 12 has a thickness which is larger than the loop height of the thin metal wires 14.
  • the sealing must be performed so as to attain excellent air tightness so that the sealing resin 15 does not enter the bottom region of the inner lead portions 13.
  • the outer lead portions 16 of the lead frame 9 are shaped so as to be exposed with being flush with the outer face of the sealing resin 15.
  • the adhesiveness between the sealing resin 15 and the lead frame 9 is ensured, and package crack is prevented from occurring, thereby enabling the reliability to be maintained.
  • the adhesiveness with the sealing resin 15 can be improved, and stress which acts on the inner lead portions 13 and due to the single-side molding structure can be relaxed, and also the adhesiveness (anchoring effect) with the sealing resin 15 can be improved. In other words, dislocation from the sealing resin 15 to the inner lead portions 13 is prevented from occurring.
  • the sealing resin 15 is formed into the single-side molding structure. According to this structure, therefore, stress by the sealing resin 15 acts on the inner lead portions 13.
  • the groove portions 19 are formed in the inner lead portions 13, and the stress acting on the inner lead portions 13 can be absorbed by the groove portions 19 so as to be relaxed. Since the connecting portions are disposed between the groove portions 19, the connecting portions are not damaged by the stress to be broken.
  • the suspension leads 10 of the lead frame 9 are subjected to the upsetting process, and the die pad portion 11 is raised to a level higher than the inner lead portions 13. Therefore, the sealing resin 15 of a thickness corresponding to the step difference of the upsetting exists below the die pad portion 11, the adhesiveness between the lead frame 9 and the sealing resin 15 can be improved, and the reliability of a product can be maintained.
  • the outer lead portions 16 are arranged so as to be embedded into the bottom face portion of the sealing resin 15 without projecting from the side face of the sealing resin 15.
  • the reliability of the outer lead portions serving as external terminals can be improved, and it is possible to provide a resin molded type semiconductor device which is miniaturized by a size corresponding to the nonprojecting structure of the outer lead portions. Even when both the faces, or the upper and lower faces of the lead frame 9 are resin-molded, the thickness of the resin of the lower face is equal to the thickness of the step difference of the upsetting.
  • the reduction of the area of the die pad portion 11, and the disposition of an opening can enhance the adhesiveness between the sealing resin 15 and the rear face of the semiconductor chip 12, and the reliability can be ensured.
  • the adhesiveness with the sealing resin can be improved, and stress which acts on the inner lead portions 13 and due to the single-side molding structure can be relaxed by the widened portion 18 and the groove portions 19 which are disposed in the surface of each of the inner lead portions 13.
  • the groove portions 19 absorb stress to the connecting portions of the thin metal wires 14 on the side of the inner lead portions 13. Therefore, the connecting portions of the thin metal wires 14 are not affected by stress, breakage of the connecting portions is prevented from occurring, stable connection is enabled, and the reliability of a product can be improved, whereby the reliability of the resin molded type semiconductor device can be improved.
  • the number of the groove portions 19 of each of the inner lead portions 13 is two.
  • the groove direction of the groove portions elongates along a side face of the semiconductor device.
  • the groove direction may be set to be any direction such as that which intersects a side face.
  • the groove portions may be formed into a mesh-like shape in which grooves elongate longitudinally and latitudinally. Both the groove portions and the widened portion are disposed. Alternatively, only one of the two kinds of portions may be disposed.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
EP98923185A 1997-06-27 1998-06-08 Resin molded type semiconductor device Expired - Lifetime EP0996962B1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP17139597 1997-06-27
JP17139597 1997-06-27
JP7371198A JP2915892B2 (ja) 1997-06-27 1998-03-23 樹脂封止型半導体装置およびその製造方法
JP7371198 1998-03-23
PCT/JP1998/002544 WO1999000826A2 (en) 1997-06-27 1998-06-08 Resin molded type semiconductor device and a method of manufacturing the same

Publications (2)

Publication Number Publication Date
EP0996962A2 EP0996962A2 (en) 2000-05-03
EP0996962B1 true EP0996962B1 (en) 2010-08-18

Family

ID=26414858

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98923185A Expired - Lifetime EP0996962B1 (en) 1997-06-27 1998-06-08 Resin molded type semiconductor device

Country Status (8)

Country Link
US (1) US6900524B1 (zh)
EP (1) EP0996962B1 (zh)
JP (1) JP2915892B2 (zh)
KR (1) KR100397539B1 (zh)
CN (2) CN100423253C (zh)
DE (1) DE69841847D1 (zh)
TW (1) TW384534B (zh)
WO (1) WO1999000826A2 (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY133357A (en) 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
JP3768762B2 (ja) * 2000-02-03 2006-04-19 ローム株式会社 樹脂パッケージ型半導体装置
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
JP4547086B2 (ja) 2000-12-25 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
JP3895570B2 (ja) 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6882048B2 (en) * 2001-03-30 2005-04-19 Dainippon Printing Co., Ltd. Lead frame and semiconductor package having a groove formed in the respective terminals for limiting a plating area
JP2003204027A (ja) 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
JP2003224239A (ja) * 2002-01-29 2003-08-08 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6841854B2 (en) 2002-04-01 2005-01-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device
KR100975692B1 (ko) * 2002-07-01 2010-08-12 가부시끼가이샤 르네사스 테크놀로지 반도체 장치
JP2004335710A (ja) * 2003-05-07 2004-11-25 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2005159103A (ja) 2003-11-27 2005-06-16 Renesas Technology Corp 半導体装置およびその製造方法
US20050167796A1 (en) * 2004-01-29 2005-08-04 Tay Kheng C. Miniaturised surface mount optoelectronic component
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package
JP2006108306A (ja) * 2004-10-04 2006-04-20 Yamaha Corp リードフレームおよびそれを用いた半導体パッケージ
US20060131708A1 (en) * 2004-12-16 2006-06-22 Ng Kee Y Packaged electronic devices, and method for making same
US8138586B2 (en) * 2005-05-06 2012-03-20 Stats Chippac Ltd. Integrated circuit package system with multi-planar paddle
JP4055175B2 (ja) * 2005-10-07 2008-03-05 ヤマハ株式会社 半導体パッケージ
JP4489791B2 (ja) * 2007-05-14 2010-06-23 株式会社ルネサステクノロジ Ｑｆｎパッケージ
JP2009032906A (ja) * 2007-07-27 2009-02-12 Seiko Instruments Inc 半導体装置パッケージ
JP5097639B2 (ja) * 2008-08-01 2012-12-12 ルネサスエレクトロニクス株式会社 リードフレーム及び半導体装置
US8072770B2 (en) * 2008-10-14 2011-12-06 Texas Instruments Incorporated Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
CN101859827A (zh) * 2009-04-07 2010-10-13 裕星企业有限公司 发光二极管
JP2010118712A (ja) * 2010-03-04 2010-05-27 Renesas Technology Corp Ｑｆｎパッケージの製造方法
JP2015153987A (ja) * 2014-02-18 2015-08-24 株式会社デンソー モールドパッケージ
JP2015177080A (ja) * 2014-03-15 2015-10-05 新日本無線株式会社 リード内蔵型回路パッケージ及びその製造方法
JP6253531B2 (ja) * 2014-06-30 2017-12-27 ルネサスエレクトロニクス株式会社 半導体装置
CN104505379A (zh) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 导线框架条及使用该导线框架条的半导体封装体
WO2016203787A1 (ja) * 2015-06-18 2016-12-22 シャープ株式会社 送風装置
CN107924884B (zh) * 2016-03-30 2022-02-18 松下知识产权经营株式会社 半导体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0628997A2 (en) * 1993-06-10 1994-12-14 Texas Instruments Incorporated Semiconductor device with small die pad and method of making same

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL159818B (nl) * 1972-04-06 1979-03-15 Philips Nv Halfgeleiderinrichting, bevattende een flexibele isolerende folie, die aan een zijde is voorzien van metalen geleider- sporen.
JPS6049089B2 (ja) 1977-03-02 1985-10-31 日本電気株式会社 Ｆｒｐアンテナレフレクタ−の製造方法
JPS6086851A (ja) * 1983-10-19 1985-05-16 Nec Corp 樹脂封止型半導体装置
JPH0612796B2 (ja) * 1984-06-04 1994-02-16 株式会社日立製作所 半導体装置
JPS611042A (ja) * 1984-06-13 1986-01-07 Toshiba Corp 半導体装置
FR2568411B1 (fr) 1984-07-30 1989-12-01 Accumulateurs Fixes Procede pour ameliorer la resistance electrique d'une jonction non soudee dans un accumulateur electrique, ou une batterie d'accumulateurs electriques et jonction obtenue par ce procede.
JPS6364351A (ja) * 1986-09-04 1988-03-22 Toshiba Corp リ−ドフレ−ム
JPS63258050A (ja) 1987-04-15 1988-10-25 Mitsubishi Electric Corp 半導体装置
JPH01106456A (ja) * 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JPH01106455A (ja) * 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US4994895A (en) * 1988-07-11 1991-02-19 Fujitsu Limited Hybrid integrated circuit package structure
JPH02201946A (ja) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd 半導体装置
JPH0485952A (ja) * 1990-07-27 1992-03-18 Fujitsu Ltd 半導体装置
JPH04123550A (ja) 1990-09-14 1992-04-23 Yaesu Musen Co Ltd データ信号のアナログ／デジタル変換方式
JPH04155854A (ja) * 1990-10-19 1992-05-28 Hitachi Ltd 半導体集積回路装置およびそれに用いるリードフレーム
JP2917575B2 (ja) * 1991-05-23 1999-07-12 株式会社日立製作所 樹脂封止型半導体装置
JPH05129473A (ja) 1991-11-06 1993-05-25 Sony Corp 樹脂封止表面実装型半導体装置
TW332348B (en) * 1992-06-23 1998-05-21 Sony Co Ltd Manufacturing method for solid state motion picture device provides a highly accurate and low cost solid state motion picture device by use of empty package made of resin.
JPH0621315A (ja) 1992-07-02 1994-01-28 Seiko Epson Corp 半導体装置用リードフレーム及び、それを用いた半導体装置
JPH0621304A (ja) 1992-07-06 1994-01-28 Seiko Epson Corp リードフレーム及び半導体装置の製造方法
JPH0685132A (ja) 1992-09-07 1994-03-25 Mitsubishi Electric Corp 半導体装置
JPH06104364A (ja) 1992-09-22 1994-04-15 Sony Corp リードフレーム、これを用いた半導体チップのモールド方法及びモールド用金型
US5389739A (en) * 1992-12-15 1995-02-14 Hewlett-Packard Company Electronic device packaging assembly
JP3136029B2 (ja) 1993-08-09 2001-02-19 株式会社日立製作所 半導体装置
JP3233507B2 (ja) * 1993-08-13 2001-11-26 株式会社東芝 半導体装置
DE69530037T2 (de) * 1994-09-22 2003-10-16 Nec Electronics Corp Automatische Bandmontage für Halbleiteranordnung
JP3309686B2 (ja) * 1995-03-17 2002-07-29 セイコーエプソン株式会社 樹脂封止型半導体装置及びその製造方法
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
US5872395A (en) * 1996-09-16 1999-02-16 International Packaging And Assembly Corporation Bent tip method for preventing vertical motion of heat spreaders during injection molding of IC packages
US5859387A (en) * 1996-11-29 1999-01-12 Allegro Microsystems, Inc. Semiconductor device leadframe die attach pad having a raised bond pad
US5869889A (en) * 1997-04-21 1999-02-09 Lsi Logic Corporation Thin power tape ball grid array package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0628997A2 (en) * 1993-06-10 1994-12-14 Texas Instruments Incorporated Semiconductor device with small die pad and method of making same

Also Published As

Publication number Publication date
CN101114629B (zh) 2011-05-11
KR100397539B1 (ko) 2003-09-13
EP0996962A2 (en) 2000-05-03
TW384534B (en) 2000-03-11
KR20010013562A (ko) 2001-02-26
CN1268246A (zh) 2000-09-27
CN100423253C (zh) 2008-10-01
JP2915892B2 (ja) 1999-07-05
WO1999000826A3 (en) 1999-05-27
DE69841847D1 (de) 2010-09-30
US6900524B1 (en) 2005-05-31
JPH1174440A (ja) 1999-03-16
WO1999000826A2 (en) 1999-01-07
CN101114629A (zh) 2008-01-30

Similar Documents

Publication Publication Date Title
EP0996962B1 (en) Resin molded type semiconductor device
US6861734B2 (en) Resin-molded semiconductor device
US6703696B2 (en) Semiconductor package
US5942794A (en) Plastic encapsulated semiconductor device and method of manufacturing the same
US6124546A (en) Integrated circuit chip package and method of making the same
US4984059A (en) Semiconductor device and a method for fabricating the same
US7049684B2 (en) Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same
US5891758A (en) Semiconductor device and method for manufacturing semiconductor device
US6861735B2 (en) Resin molded type semiconductor device and a method of manufacturing the same
KR20040036643A (ko) 리드프레임, 수지봉입형 반도체장치 및 그 제조방법
US6300685B1 (en) Semiconductor package
EP0732744B1 (en) Resin sealing type semiconductor device and method of making the same
JP2009544159A (ja) 平坦な構造を有するモジュールと構成部品の設置方法
US20030003627A1 (en) Method for manufacturing a resin-sealed semiconductor device
US6774479B2 (en) Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for producing the electronic device
US6246117B1 (en) Semiconductor device comprised of a ball grid array and an insulating film with preformed land openings
JPH07307409A (ja) 半導体装置及びその製造方法
KR200211272Y1 (ko) 칩 사이즈 패키지
JP4103764B2 (ja) リードフレーム
KR19990085110A (ko) 본딩패드 인터커넥트형 멀티 칩 패키지
KR19990003760U (ko) 반도체 패키지 및 인쇄회로기판과의 결합구조
JPH0824157B2 (ja) 半導体装置の製造方法
JPH04159791A (ja) 混成集積回路
JPH06120372A (ja) セラミック型半導体装置
JP2002246533A (ja) 樹脂封止型半導体装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19991005

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

17Q First examination report despatched

Effective date: 20010724

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: PANASONIC CORPORATION

RTI1 Title (correction)

Free format text: RESIN MOLDED TYPE SEMICONDUCTOR DEVICE

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 69841847

Country of ref document: DE

Date of ref document: 20100930

Kind code of ref document: P

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20110519

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20110608

Year of fee payment: 14

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 69841847

Country of ref document: DE

Effective date: 20110519

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20110601

Year of fee payment: 14

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120608

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69841847

Country of ref document: DE

Effective date: 20130101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20130101

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120608