DE69534483T2 - Leiterrahmen und Halbleiterbauelement - Google Patents

Leiterrahmen und Halbleiterbauelement Download PDF

Info

Publication number
DE69534483T2
DE69534483T2 DE1995634483 DE69534483T DE69534483T2 DE 69534483 T2 DE69534483 T2 DE 69534483T2 DE 1995634483 DE1995634483 DE 1995634483 DE 69534483 T DE69534483 T DE 69534483T DE 69534483 T2 DE69534483 T2 DE 69534483T2
Authority
DE
Germany
Prior art keywords
terminals
lead frame
connections
web
carrier plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1995634483
Other languages
German (de)
English (en)
Other versions
DE69534483D1 (de
Inventor
Naotaka Niihari-gun Tanaka
Akihiro Niihari-gun Yaguchi
Makoto Kitano
Tatsuya Nagata
Tetsuo Niihari-gun Kumazawa
Atsushi Nakamura
Hiromichi Suzuki
Masayoshi Tsugane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69534483D1 publication Critical patent/DE69534483D1/de
Publication of DE69534483T2 publication Critical patent/DE69534483T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE1995634483 1994-05-16 1995-05-12 Leiterrahmen und Halbleiterbauelement Expired - Fee Related DE69534483T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10044494 1994-05-16
JP10044494 1994-05-16

Publications (2)

Publication Number Publication Date
DE69534483D1 DE69534483D1 (de) 2006-02-09
DE69534483T2 true DE69534483T2 (de) 2006-07-06

Family

ID=14274105

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1995634483 Expired - Fee Related DE69534483T2 (de) 1994-05-16 1995-05-12 Leiterrahmen und Halbleiterbauelement

Country Status (7)

Country Link
US (2) US5637914A (show.php)
EP (1) EP0683518B1 (show.php)
KR (1) KR100225333B1 (show.php)
CN (1) CN1097312C (show.php)
DE (1) DE69534483T2 (show.php)
MY (1) MY114386A (show.php)
TW (1) TW293167B (show.php)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2928120B2 (ja) * 1995-01-18 1999-08-03 日本電気株式会社 樹脂封止型半導体装置用リードフレームおよび樹脂封止型半導体装置の製造方法
JPH0951067A (ja) * 1995-08-08 1997-02-18 Sony Corp リードフレーム
JPH09129686A (ja) * 1995-11-06 1997-05-16 Toshiba Microelectron Corp テープキャリヤ及びその実装構造
KR100214480B1 (ko) * 1996-05-17 1999-08-02 구본준 반도체 패키지용 리드 프레임
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US5929512A (en) * 1997-03-18 1999-07-27 Jacobs; Richard L. Urethane encapsulated integrated circuits and compositions therefor
JPH10303352A (ja) * 1997-04-22 1998-11-13 Toshiba Corp 半導体装置および半導体装置の製造方法
US6305921B1 (en) * 1999-07-12 2001-10-23 Accu-Mold Corp. Saw tooth mold
JP2001156212A (ja) 1999-09-16 2001-06-08 Nec Corp 樹脂封止型半導体装置及びその製造方法
JP2002343816A (ja) 2001-05-18 2002-11-29 Lintec Corp 樹脂タイバー形成用テープ、樹脂タイバー、樹脂タイバー付リードフレーム、樹脂封止型半導体装置およびその製造方法
JP4054188B2 (ja) * 2001-11-30 2008-02-27 富士通株式会社 半導体装置
CN100536121C (zh) * 2001-12-14 2009-09-02 株式会社瑞萨科技 半导体器件及其制造方法
JP3812447B2 (ja) * 2002-01-28 2006-08-23 富士電機デバイステクノロジー株式会社 樹脂封止形半導体装置
JP2005086014A (ja) * 2003-09-09 2005-03-31 Oki Electric Ind Co Ltd 半導体装置、及び半導体装置の製造方法
JP4595835B2 (ja) * 2006-03-07 2010-12-08 株式会社日立製作所 鉛フリーはんだを用いたリード付き電子部品
US8148825B2 (en) * 2007-06-05 2012-04-03 Stats Chippac Ltd. Integrated circuit package system with leadfinger
US8648458B2 (en) * 2009-12-18 2014-02-11 Nxp B.V. Leadframe circuit and method therefor
JP5549612B2 (ja) 2011-01-31 2014-07-16 三菱電機株式会社 半導体装置の製造方法
US9082759B2 (en) * 2012-11-27 2015-07-14 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
EP2948709B1 (en) * 2013-01-25 2016-10-05 Koninklijke Philips N.V. Lighting assembly and method for manufacturing a lighting assembly
US20140208689A1 (en) 2013-01-25 2014-07-31 Renee Joyal Hypodermic syringe assist apparatus and method
CN108735701B (zh) 2017-04-13 2021-12-24 恩智浦美国有限公司 具有用于包封期间的毛刺缓解的虚设引线的引线框架
JP7182374B2 (ja) * 2017-05-15 2022-12-02 新光電気工業株式会社 リードフレーム及びその製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192058A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device
JPS5828841A (ja) * 1981-08-14 1983-02-19 Toshiba Corp 樹脂封止型半導体装置の製造方法
US4899207A (en) * 1986-08-27 1990-02-06 Digital Equipment Corporation Outer lead tape automated bonding
JPH01187842A (ja) * 1988-01-21 1989-07-27 Toshiba Corp 半導体装置の製造方法
JPH02122660A (ja) * 1988-11-01 1990-05-10 Nec Corp プラスチックパッケージ
JPH02220468A (ja) * 1989-02-21 1990-09-03 Oki Electric Ind Co Ltd 半導体装置用リードフレーム
JP2685582B2 (ja) * 1989-05-26 1997-12-03 株式会社日立製作所 リードフレーム及びこれを用いた半導体装置
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
JPH03136267A (ja) * 1989-10-20 1991-06-11 Texas Instr Japan Ltd 半導体装置及びその製造方法
US5258331A (en) * 1989-10-20 1993-11-02 Texas Instruments Incorporated Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars
JPH0491464A (ja) * 1990-08-01 1992-03-24 Ibiden Co Ltd リードフレーム
JPH04133459A (ja) * 1990-09-26 1992-05-07 Nec Corp リードフレーム
JPH04206560A (ja) * 1990-11-30 1992-07-28 New Japan Radio Co Ltd 半導体装置の製造方法
JPH04255260A (ja) * 1991-02-07 1992-09-10 Fujitsu Ltd リードフレーム及び半導体装置の製造方法
JP2959874B2 (ja) * 1991-07-02 1999-10-06 大日本印刷株式会社 リードフレームの製造方法
JPH05218283A (ja) * 1992-02-03 1993-08-27 Nec Corp 半導体装置
US5352633A (en) * 1992-06-02 1994-10-04 Texas Instruments Incorporated Semiconductor lead frame lead stabilization
JP3246769B2 (ja) * 1992-07-15 2002-01-15 株式会社日立製作所 半導体装置及びその製造方法
JPH0799768B2 (ja) * 1992-08-24 1995-10-25 徹也 北城 リードフレームへのピン保持部の形成方法、および形成装置
US5281851A (en) * 1992-10-02 1994-01-25 Hewlett-Packard Company Integrated circuit packaging with reinforced leads
US5336564A (en) * 1993-12-06 1994-08-09 Grumman Aerospace Corporation Miniature keeper bar
US5422313A (en) * 1994-05-03 1995-06-06 Texas Instruments Incorporated Integrated circuit device and manufacturing method using photoresist lead covering

Also Published As

Publication number Publication date
CN1097312C (zh) 2002-12-25
KR100225333B1 (ko) 1999-10-15
US5837567A (en) 1998-11-17
TW293167B (show.php) 1996-12-11
EP0683518B1 (en) 2005-09-28
US5637914A (en) 1997-06-10
MY114386A (en) 2002-10-31
DE69534483D1 (de) 2006-02-09
EP0683518A2 (en) 1995-11-22
CN1121261A (zh) 1996-04-24
EP0683518A3 (en) 1998-09-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee