JP5549612B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5549612B2 JP5549612B2 JP2011017877A JP2011017877A JP5549612B2 JP 5549612 B2 JP5549612 B2 JP 5549612B2 JP 2011017877 A JP2011017877 A JP 2011017877A JP 2011017877 A JP2011017877 A JP 2011017877A JP 5549612 B2 JP5549612 B2 JP 5549612B2
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- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000011347 resin Substances 0.000 claims description 40
- 229920005989 resin Polymers 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 22
- 238000007789 sealing Methods 0.000 claims description 10
- 238000009933 burial Methods 0.000 claims description 2
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本発明の実施の形態1に係る半導体装置の製造方法について図面を参照して説明する。図1は、本発明の実施の形態1で用いるリードフレームを示す上面図である。リードフレーム1は、ダイパッド2と、リード端子3と、タイバー4とを有する。リードフレーム1の領域は、後の工程で樹脂封止されないパッケージ外部領域5と、後の工程で樹脂封止されるパッケージ内部領域6とに分けられる。
図10は、本発明の実施の形態2に係る半導体装置の製造方法を説明するための断面図である。本実施の形態では、パッケージ外部領域5においてリードフレーム1のダレ面9が設けられた部分も面取り加工する。これにより、リード端子3間の最短距離に位置するリード端子3の側面の面積を実施の形態1よりも減少することができる。従って、リード端子3間の放電を更に抑制することができる。
図11は本発明の実施の形態3に係る半導体装置の製造方法を説明するための上面図であり、図12はその一部を拡大した断面図である。
図13は、本発明の実施の形態4に係る半導体装置の製造方法を説明するための断面図である。実施の形態1〜3と同様に面取り加工及び樹脂止した後に、リードフレーム1の側面に樹脂バリ13が設けられた部分を曲げ加工する。これにより、リードフレーム1の側面に付着した樹脂バリ13に応力が発生するため、樹脂バリ13の除去が容易となる。
5 パッケージ外部領域
6 パッケージ内部領域
7 カエリ面
8 破断面
9 ダレ面
10 半導体素子
12 モールド樹脂(樹脂)
13 樹脂バリ
14 上金型(モールド金型)
15 下金型(モールド金型)
Claims (3)
- パッケージ外部領域とパッケージ内部領域を有し、側面の上端にカエリ面が設けられ、前記側面の上端近傍に破断面が設けられたリードフレームを用いる半導体装置の製造方法であって、
前記パッケージ外部領域において前記リードフレームの前記側面の前記上端を面取り加工する工程と、
前記パッケージ内部領域において前記リードフレーム上に半導体素子を搭載して樹脂で封止する工程と、
面取り加工及び樹脂封止の後に、前記パッケージ外部領域において前記リードフレームの前記側面に設けられた樹脂バリを除去する工程とを備え、
前記樹脂で封止する際にモールド金型を用い、
前記モールド金型により前記面取り加工も同時に行うことを特徴とする半導体装置の製造方法。 - 前記リードフレームの前記側面の下端を面取り加工する工程を更に備えることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記面取り加工し、前記樹脂で封止した後に、前記リードフレームの前記側面に前記樹脂バリが設けられた部分を曲げ加工することを特徴とする請求項1又は2に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011017877A JP5549612B2 (ja) | 2011-01-31 | 2011-01-31 | 半導体装置の製造方法 |
US13/213,593 US8518751B2 (en) | 2011-01-31 | 2011-08-19 | Method for manufacturing semiconductor device including removing a resin burr |
DE102011086312.5A DE102011086312B4 (de) | 2011-01-31 | 2011-11-14 | Verfahren zum Herstellen einer Halbleitervorrichtung |
CN201110364928.4A CN102623360B (zh) | 2011-01-31 | 2011-11-17 | 半导体装置的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011017877A JP5549612B2 (ja) | 2011-01-31 | 2011-01-31 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012160517A JP2012160517A (ja) | 2012-08-23 |
JP5549612B2 true JP5549612B2 (ja) | 2014-07-16 |
Family
ID=46511491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011017877A Expired - Fee Related JP5549612B2 (ja) | 2011-01-31 | 2011-01-31 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8518751B2 (ja) |
JP (1) | JP5549612B2 (ja) |
CN (1) | CN102623360B (ja) |
DE (1) | DE102011086312B4 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6597393B2 (ja) * | 2016-02-29 | 2019-10-30 | 住友電装株式会社 | 樹脂成形品とその製造方法 |
US11152275B2 (en) | 2016-03-07 | 2021-10-19 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
WO2017168537A1 (ja) * | 2016-03-29 | 2017-10-05 | 三菱電機株式会社 | 樹脂封止型電力半導体装置の製造方法 |
EP3471220A1 (en) * | 2017-10-16 | 2019-04-17 | TE Connectivity Germany GmbH | Bent electric contact element with chamfered edges and method for its manufacture |
US11543466B2 (en) | 2018-03-24 | 2023-01-03 | Melexis Technologies Sa | Magnetic sensor component and assembly |
EP3544394A1 (en) | 2018-03-24 | 2019-09-25 | Melexis Technologies SA | Integrated circuit lead frame design and method |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60123047A (ja) * | 1983-12-07 | 1985-07-01 | Toshiba Corp | 半導体装置 |
JPS60261163A (ja) * | 1984-06-07 | 1985-12-24 | Shinko Electric Ind Co Ltd | リードフレームの製造方法 |
JPS62198143A (ja) * | 1986-02-26 | 1987-09-01 | Shinko Electric Ind Co Ltd | リ−ドフレ−ム |
JPS62247553A (ja) * | 1986-04-18 | 1987-10-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS63151056A (ja) | 1986-12-16 | 1988-06-23 | Matsushita Electronics Corp | リ−ドフレ−ムの製造方法 |
JPS63197363A (ja) | 1987-02-12 | 1988-08-16 | Goto Seisakusho:Kk | 半導体装置の製造方法 |
JP2606736B2 (ja) * | 1989-01-31 | 1997-05-07 | 株式会社三井ハイテック | リードフレームの製造方法 |
JPH03275224A (ja) | 1990-03-23 | 1991-12-05 | Hitachi Cable Ltd | 順送金型によるリードフレームの打抜き加工方法 |
JPH0442565A (ja) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | 半導体パッケージ |
JPH04164356A (ja) | 1990-10-29 | 1992-06-10 | Nec Corp | リードフレーム |
JPH06291244A (ja) * | 1993-03-31 | 1994-10-18 | Kawasaki Steel Corp | リードフレームおよび半導体装置 |
US5637914A (en) | 1994-05-16 | 1997-06-10 | Hitachi, Ltd. | Lead frame and semiconductor device encapsulated by resin |
GB2296992A (en) * | 1995-01-05 | 1996-07-17 | Int Rectifier Co Ltd | Electrode configurations in surface-mounted devices |
JPH09276952A (ja) | 1996-04-15 | 1997-10-28 | Apic Yamada Kk | リードフレーム打ち抜き用プレス加工金型 |
US5886397A (en) * | 1996-09-05 | 1999-03-23 | International Rectifier Corporation | Crushable bead on lead finger side surface to improve moldability |
DE19736895A1 (de) | 1996-09-05 | 1998-04-16 | Int Rectifier Corp | Gehäuse für Halbleiterbauteile |
US5939775A (en) | 1996-11-05 | 1999-08-17 | Gcb Technologies, Llc | Leadframe structure and process for packaging intergrated circuits |
JP3862410B2 (ja) * | 1998-05-12 | 2006-12-27 | 三菱電機株式会社 | 半導体装置の製造方法及びその構造 |
TW428295B (en) * | 1999-02-24 | 2001-04-01 | Matsushita Electronics Corp | Resin-sealing semiconductor device, the manufacturing method and the lead frame thereof |
-
2011
- 2011-01-31 JP JP2011017877A patent/JP5549612B2/ja not_active Expired - Fee Related
- 2011-08-19 US US13/213,593 patent/US8518751B2/en not_active Expired - Fee Related
- 2011-11-14 DE DE102011086312.5A patent/DE102011086312B4/de not_active Expired - Fee Related
- 2011-11-17 CN CN201110364928.4A patent/CN102623360B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8518751B2 (en) | 2013-08-27 |
CN102623360B (zh) | 2014-10-22 |
JP2012160517A (ja) | 2012-08-23 |
CN102623360A (zh) | 2012-08-01 |
DE102011086312A1 (de) | 2012-08-02 |
US20120196405A1 (en) | 2012-08-02 |
DE102011086312B4 (de) | 2016-03-24 |
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