DE69528409T2 - Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung

Info

Publication number
DE69528409T2
DE69528409T2 DE69528409T DE69528409T DE69528409T2 DE 69528409 T2 DE69528409 T2 DE 69528409T2 DE 69528409 T DE69528409 T DE 69528409T DE 69528409 T DE69528409 T DE 69528409T DE 69528409 T2 DE69528409 T2 DE 69528409T2
Authority
DE
Germany
Prior art keywords
layer
organic material
conductors
dielectric
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69528409T
Other languages
German (de)
English (en)
Other versions
DE69528409D1 (de
Inventor
Robert H. Havemann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69528409D1 publication Critical patent/DE69528409D1/de
Application granted granted Critical
Publication of DE69528409T2 publication Critical patent/DE69528409T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69528409T 1994-04-28 1995-04-28 Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung Expired - Fee Related DE69528409T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/234,100 US5565384A (en) 1994-04-28 1994-04-28 Self-aligned via using low permittivity dielectric

Publications (2)

Publication Number Publication Date
DE69528409D1 DE69528409D1 (de) 2002-11-07
DE69528409T2 true DE69528409T2 (de) 2003-08-21

Family

ID=22879931

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528409T Expired - Fee Related DE69528409T2 (de) 1994-04-28 1995-04-28 Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung

Country Status (6)

Country Link
US (1) US5565384A (https=)
EP (1) EP0680084B1 (https=)
JP (1) JPH0851154A (https=)
KR (1) KR950034532A (https=)
DE (1) DE69528409T2 (https=)
TW (1) TW299484B (https=)

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Also Published As

Publication number Publication date
JPH0851154A (ja) 1996-02-20
TW299484B (https=) 1997-03-01
US5565384A (en) 1996-10-15
DE69528409D1 (de) 2002-11-07
EP0680084B1 (en) 2002-10-02
KR950034532A (https=) 1995-12-28
EP0680084A1 (en) 1995-11-02

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