JP5134193B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5134193B2 JP5134193B2 JP2005206370A JP2005206370A JP5134193B2 JP 5134193 B2 JP5134193 B2 JP 5134193B2 JP 2005206370 A JP2005206370 A JP 2005206370A JP 2005206370 A JP2005206370 A JP 2005206370A JP 5134193 B2 JP5134193 B2 JP 5134193B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- conductive layer
- layer film
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
記第2導電層は前記第1導電層よりも高い位置に形成されている半導体基板と、前記第1
導電層及び前記第2導電層を覆うように前記半導体基板上に形成されるシリコン窒化膜と
、塗布法により形成されるポリアリレン系の有機系絶縁材料からなり、その表面の高さが
、前記シリコン窒化膜をストッパ膜としたCMP法を用いたことにより前記シリコン窒化
膜の高さと略一致している第1層膜及びこの第1層膜上にCVD法により形成される無機
系絶縁材料からなる第2層膜の少なくとも2層構造を有し前記シリコン窒化膜を介して前
記第1導電層及び前記第2導電層を覆うように形成される層間絶縁膜と、前記第2層膜を
貫通して前記第2導電層に達する第1コンタクトホールと、前記第1層膜及び前記第2層
膜を貫通して前記第1導電層に達する第2コンタクトホールとを備えたことを特徴とする
。
1導電層及びこの第1導電層よりも高い位置に存在する第2導電層を形成するステップと
、 前記第1導電層上及び第2導電層上を含む半導体基板上にシリコン窒化膜を形成する
ステップと、塗布法により形成されるポリアリレン系の有機系絶縁材料からなる第1層膜
を前記シリコン窒化膜を介して前記第1導電層及び前記第2導電層を覆うように形成した
後、前記第1層膜を前記シリコン窒化膜をストッパ膜としたCMP法により平坦化し、こ
れにより前記第1層膜の表面の高さが、前記シリコン窒化膜の高さと略一致するようにし
、続いて前記第1層膜上に無機系絶縁材料からなる第2層膜をCVD法により形成し、前
記第1層膜及び前記第2層膜の少なくとも2層構造を有する層間絶縁膜を形成するステッ
プと、 第1のエッチング条件により前記第2層膜をエッチングした後前記第1のエッチ
ング条件とは異なるエッチング条件により第1層膜をエッチングして、前記第2層膜を貫
通して前記第2導電層に達する第1コンタクトホールと、前記第1層膜及び前記第2層膜
を貫通して前記第1導電層に達する第2コンタクトホールとを形成する工程とを備えたこ
とを特徴とする。
Claims (4)
- 第1導電層及び第2導電層を表面側に形成され前記第2導電層は前記第1導電層よりも
高い位置に形成されている半導体基板と、
前記第1導電層及び前記第2導電層を覆うように前記半導体基板上に形成されるシリコ
ン窒化膜と、
塗布法により形成されるポリアリレン系の有機系絶縁材料からなり、その表面の高さが
、前記シリコン窒化膜をストッパ膜としたCMP法を用いたことにより前記シリコン窒化
膜の高さと略一致している第1層膜及びこの第1層膜上にCVD法により形成される無機
系絶縁材料からなる第2層膜の少なくとも2層構造を有し前記シリコン窒化膜を介して前
記第1導電層及び前記第2導電層を覆うように形成される層間絶縁膜と、
前記第2層膜を貫通して前記第2導電層に達する第1コンタクトホールと、
前記第1層膜及び前記第2層膜を貫通して前記第1導電層に達する第2コンタクトホー
ルと
を備えたことを特徴とする半導体装置。 - 前記CMP法は、有機系材料のスラリを用いて実行される請求項1記載の半導体装置。
- 半導体基板の表面側に、第1導電層及びこの第1導電層よりも高い位置に存在する第2
導電層を形成するステップと、
前記第1導電層上及び第2導電層上を含む半導体基板上にシリコン窒化膜を形成するス
テップと、
塗布法により形成されるポリアリレン系の有機系絶縁材料からなる第1層膜を前記シリ
コン窒化膜を介して前記第1導電層及び前記第2導電層を覆うように形成した後、前記第
1層膜を前記シリコン窒化膜をストッパ膜としたCMP法により平坦化し、これにより前
記第1層膜の表面の高さが、前記シリコン窒化膜の高さと略一致するようにし、続いて前
記第1層膜上に無機系絶縁材料からなる第2層膜をCVD法により形成し、前記第1層膜
及び前記第2層膜の少なくとも2層構造を有する層間絶縁膜を形成するステップと、
第1のエッチング条件により前記第2層膜をエッチングした後前記第1のエッチング条
件とは異なるエッチング条件により第1層膜をエッチングして、前記第2層膜を貫通して
前記第2導電層に達する第1コンタクトホールと、前記第1層膜及び前記第2層膜を貫通
して前記第1導電層に達する第2コンタクトホールとを形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記CMP法は、有機系材料のスラリを用いて実行される請求項3記載の半導体装置の
製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005206370A JP5134193B2 (ja) | 2005-07-15 | 2005-07-15 | 半導体装置及びその製造方法 |
US11/435,808 US20070013076A1 (en) | 2005-07-15 | 2006-05-18 | Semiconductor device and method of manufacturing thereof |
US12/010,935 US7701004B2 (en) | 2005-07-15 | 2008-01-31 | Semiconductor device and method of manufacturing thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005206370A JP5134193B2 (ja) | 2005-07-15 | 2005-07-15 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007027343A JP2007027343A (ja) | 2007-02-01 |
JP5134193B2 true JP5134193B2 (ja) | 2013-01-30 |
Family
ID=37660951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005206370A Expired - Fee Related JP5134193B2 (ja) | 2005-07-15 | 2005-07-15 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070013076A1 (ja) |
JP (1) | JP5134193B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8258057B2 (en) * | 2006-03-30 | 2012-09-04 | Intel Corporation | Copper-filled trench contact for transistor performance improvement |
DE102007030058B3 (de) * | 2007-06-29 | 2008-12-24 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung eines dielektrischen Zwischenschichtmaterials mit erhöhter Zuverlässigkeit über einer Struktur, die dichtliegende Leitungen aufweist |
US8013426B2 (en) * | 2007-12-28 | 2011-09-06 | Intel Corporation | Transistor having raised source/drain self-aligned contacts and method of forming same |
JP2011082235A (ja) * | 2009-10-05 | 2011-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
CN102157437B (zh) * | 2010-02-11 | 2013-12-25 | 中国科学院微电子研究所 | 半导体结构的形成方法 |
US9779984B1 (en) | 2016-03-25 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming trenches with different depths |
DE102016114724B4 (de) | 2016-03-25 | 2021-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung |
FR3061354B1 (fr) * | 2016-12-22 | 2021-06-11 | Commissariat Energie Atomique | Procede de realisation de composant comprenant des materiaux iii-v et des contacts compatibles de filiere silicium |
JP7069605B2 (ja) | 2017-08-29 | 2022-05-18 | 富士電機株式会社 | 半導体装置の製造方法 |
CN108417533B (zh) * | 2018-04-13 | 2021-04-13 | 上海华力集成电路制造有限公司 | 接触孔的制造方法 |
WO2022217608A1 (zh) * | 2021-04-16 | 2022-10-20 | 京东方科技集团股份有限公司 | 一种驱动背板、其制作方法及发光基板 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0296707A1 (en) * | 1987-06-12 | 1988-12-28 | Hewlett-Packard Company | Incorporation of dielectric layers in a semiconductor |
JPH01215044A (ja) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | 層間膜への透孔の形成方法 |
JPH0745616A (ja) * | 1993-07-29 | 1995-02-14 | Nec Corp | 半導体装置の製造方法 |
JP2555947B2 (ja) * | 1993-08-31 | 1996-11-20 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH07122634A (ja) * | 1993-10-20 | 1995-05-12 | Sanyo Electric Co Ltd | 半導体装置 |
US5565384A (en) * | 1994-04-28 | 1996-10-15 | Texas Instruments Inc | Self-aligned via using low permittivity dielectric |
JPH09283519A (ja) * | 1996-04-08 | 1997-10-31 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH11204474A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | フッ素を含む膜の研磨方法 |
JP4048618B2 (ja) | 1998-10-07 | 2008-02-20 | ソニー株式会社 | 半導体装置の製造方法 |
JP3449998B2 (ja) | 2000-10-05 | 2003-09-22 | 沖電気工業株式会社 | 半導体装置におけるコンタクトホールの形成方法 |
JP3969698B2 (ja) * | 2001-05-21 | 2007-09-05 | 株式会社半導体エネルギー研究所 | 発光装置の作製方法 |
JP2003197878A (ja) * | 2001-10-15 | 2003-07-11 | Hitachi Ltd | メモリ半導体装置およびその製造方法 |
TWI250558B (en) * | 2003-10-23 | 2006-03-01 | Hynix Semiconductor Inc | Method for fabricating semiconductor device with fine patterns |
-
2005
- 2005-07-15 JP JP2005206370A patent/JP5134193B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-18 US US11/435,808 patent/US20070013076A1/en not_active Abandoned
-
2008
- 2008-01-31 US US12/010,935 patent/US7701004B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2007027343A (ja) | 2007-02-01 |
US20080211030A1 (en) | 2008-09-04 |
US20070013076A1 (en) | 2007-01-18 |
US7701004B2 (en) | 2010-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5134193B2 (ja) | 半導体装置及びその製造方法 | |
KR102606765B1 (ko) | 비아 플러그를 갖는 반도체 소자 및 그 형성 방법 | |
TWI387049B (zh) | 半導體積體電路裝置之製造方法 | |
JP5106933B2 (ja) | 半導体装置 | |
US7687915B2 (en) | Semiconductor device having crack stop structure | |
JP2006190839A (ja) | 半導体装置及びその製造方法 | |
US10276500B2 (en) | Enhancing barrier in air gap technology | |
US8703606B2 (en) | Method for manufacturing semiconductor device having a wiring structure | |
US7521357B2 (en) | Methods of forming metal wiring in semiconductor devices using etch stop layers | |
US10170423B2 (en) | Metal cap integration by local alloying | |
US20220352071A1 (en) | Interconnection structure of integrated circuit semiconductor device | |
US10950541B2 (en) | Semiconductor device | |
JP2006351732A (ja) | 半導体装置の製造方法 | |
JP2006114724A (ja) | 半導体装置及びその製造方法 | |
JP2010171291A (ja) | 半導体装置および半導体装置の製造方法 | |
JP5424551B2 (ja) | 半導体装置 | |
KR101095998B1 (ko) | 반도체 소자의 형성 방법 | |
JP2008277546A (ja) | 半導体装置 | |
JP2009054879A (ja) | 集積回路の製造方法 | |
WO2011030476A1 (ja) | 半導体装置の製造方法 | |
JP4214922B2 (ja) | 半導体装置 | |
US20110108987A1 (en) | Semiconductor device | |
KR20070055910A (ko) | 이중 다마신 기술을 사용하여 비아콘택 구조체를 형성하는방법 | |
KR20100043906A (ko) | 국부연결배선을 이용한 반도체장치 제조 방법 | |
JP2004273611A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080609 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100318 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100420 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100621 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20101207 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110307 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110315 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20110715 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20111125 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20111205 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120404 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120911 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121109 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151116 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151116 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |