DE69221188T2 - Feldeffekttransistorstruktur und Verfahren zur Herstellung - Google Patents

Feldeffekttransistorstruktur und Verfahren zur Herstellung

Info

Publication number
DE69221188T2
DE69221188T2 DE69221188T DE69221188T DE69221188T2 DE 69221188 T2 DE69221188 T2 DE 69221188T2 DE 69221188 T DE69221188 T DE 69221188T DE 69221188 T DE69221188 T DE 69221188T DE 69221188 T2 DE69221188 T2 DE 69221188T2
Authority
DE
Germany
Prior art keywords
manufacture
field effect
effect transistor
transistor structure
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221188T
Other languages
English (en)
Other versions
DE69221188D1 (de
Inventor
Zamanian Mehdi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69221188D1 publication Critical patent/DE69221188D1/de
Publication of DE69221188T2 publication Critical patent/DE69221188T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
DE69221188T 1991-04-01 1992-04-01 Feldeffekttransistorstruktur und Verfahren zur Herstellung Expired - Fee Related DE69221188T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/678,018 US5171700A (en) 1991-04-01 1991-04-01 Field effect transistor structure and method

Publications (2)

Publication Number Publication Date
DE69221188D1 DE69221188D1 (de) 1997-09-04
DE69221188T2 true DE69221188T2 (de) 1997-12-18

Family

ID=24721048

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221188T Expired - Fee Related DE69221188T2 (de) 1991-04-01 1992-04-01 Feldeffekttransistorstruktur und Verfahren zur Herstellung

Country Status (4)

Country Link
US (2) US5171700A (de)
EP (1) EP0507567B1 (de)
JP (1) JPH05102185A (de)
DE (1) DE69221188T2 (de)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424234A (en) * 1991-06-13 1995-06-13 Goldstar Electron Co., Ltd. Method of making oxide semiconductor field effect transistor
US5320974A (en) * 1991-07-25 1994-06-14 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor transistor device by implanting punch through stoppers
US5500379A (en) * 1993-06-25 1996-03-19 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
US6278162B1 (en) * 1993-06-30 2001-08-21 Integrated Device Technology, Inc. ESD protection for LDD devices
US5308780A (en) * 1993-07-22 1994-05-03 United Microelectronics Corporation Surface counter-doped N-LDD for high hot carrier reliability
US5463237A (en) * 1993-11-04 1995-10-31 Victor Company Of Japan, Ltd. MOSFET device having depletion layer
JP2806234B2 (ja) * 1993-12-13 1998-09-30 日本電気株式会社 半導体装置及びその製造方法
US5427964A (en) * 1994-04-04 1995-06-27 Motorola, Inc. Insulated gate field effect transistor and method for fabricating
US5482878A (en) * 1994-04-04 1996-01-09 Motorola, Inc. Method for fabricating insulated gate field effect transistor having subthreshold swing
US5441906A (en) * 1994-04-04 1995-08-15 Motorola, Inc. Insulated gate field effect transistor having a partial channel and method for fabricating
JP3256084B2 (ja) * 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
US5420057A (en) * 1994-06-30 1995-05-30 International Business Machines Corporation Simplified contact method for high density CMOS
JPH0831957A (ja) * 1994-07-19 1996-02-02 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US5650340A (en) * 1994-08-18 1997-07-22 Sun Microsystems, Inc. Method of making asymmetric low power MOS devices
KR960026960A (ko) * 1994-12-16 1996-07-22 리 패치 비대칭 저전력 모스(mos) 소자
JP2792459B2 (ja) * 1995-03-31 1998-09-03 日本電気株式会社 半導体装置の製造方法
JPH08330590A (ja) * 1995-06-05 1996-12-13 Motorola Inc 絶縁ゲート電界効果トランジスタ構造およびその製造方法
US5675166A (en) * 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6004854A (en) 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US5719425A (en) * 1996-01-31 1998-02-17 Micron Technology, Inc. Multiple implant lightly doped drain (MILDD) field effect transistor
KR100214841B1 (ko) * 1996-03-29 1999-08-02 김주용 반도체 소자 및 그의 제조방법
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US7064376B2 (en) * 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5874340A (en) * 1996-07-17 1999-02-23 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls
US5877050A (en) * 1996-09-03 1999-03-02 Advanced Micro Devices, Inc. Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
US6051471A (en) * 1996-09-03 2000-04-18 Advanced Micro Devices, Inc. Method for making asymmetrical N-channel and symmetrical P-channel devices
US5677224A (en) * 1996-09-03 1997-10-14 Advanced Micro Devices, Inc. Method of making asymmetrical N-channel and P-channel devices
US5648286A (en) * 1996-09-03 1997-07-15 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
US5654215A (en) * 1996-09-13 1997-08-05 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor
KR100205320B1 (ko) * 1996-10-25 1999-07-01 구본준 모스펫 및 그 제조방법
US5763311A (en) * 1996-11-04 1998-06-09 Advanced Micro Devices, Inc. High performance asymmetrical MOSFET structure and method of making the same
US5766969A (en) * 1996-12-06 1998-06-16 Advanced Micro Devices, Inc. Multiple spacer formation/removal technique for forming a graded junction
US5847428A (en) * 1996-12-06 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit gate conductor which uses layered spacers to produce a graded junction
US5869879A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
US5869866A (en) 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
US5834355A (en) * 1996-12-31 1998-11-10 Intel Corporation Method for implanting halo structures using removable spacer
US5793089A (en) * 1997-01-10 1998-08-11 Advanced Micro Devices, Inc. Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon
US5895955A (en) * 1997-01-10 1999-04-20 Advanced Micro Devices, Inc. MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US5998274A (en) * 1997-04-10 1999-12-07 Micron Technology, Inc. Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor
US5923982A (en) * 1997-04-21 1999-07-13 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
US5736446A (en) * 1997-05-21 1998-04-07 Powerchip Semiconductor Corp. Method of fabricating a MOS device having a gate-side air-gap structure
JPH1145995A (ja) * 1997-07-25 1999-02-16 Nec Kyushu Ltd 半導体装置およびその製造方法
US6004849A (en) * 1997-08-15 1999-12-21 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source
US5904529A (en) * 1997-08-25 1999-05-18 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate
US6137137A (en) * 1997-09-05 2000-10-24 Advanced Micro Devices, Inc. CMOS semiconductor device comprising graded N-LDD junctions with increased HCI lifetime
US6096588A (en) * 1997-11-01 2000-08-01 Advanced Micro Devices, Inc. Method of making transistor with selectively doped channel region for threshold voltage control
US6025232A (en) 1997-11-12 2000-02-15 Micron Technology, Inc. Methods of forming field effect transistors and related field effect transistor constructions
KR100260044B1 (ko) * 1997-11-25 2000-07-01 윤종용 고속/고성능 모스 트랜지스터 및 그 제조방법
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6232166B1 (en) * 1998-11-06 2001-05-15 Advanced Micro Devices, Inc. CMOS processing employing zero degree halo implant for P-channel transistor
US6211023B1 (en) * 1998-11-12 2001-04-03 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor
US6204138B1 (en) * 1999-03-02 2001-03-20 Advanced Micro Devices, Inc. Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects
US6686629B1 (en) 1999-08-18 2004-02-03 International Business Machines Corporation SOI MOSFETS exhibiting reduced floating-body effects
JP3831598B2 (ja) * 2000-10-19 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
JP5073136B2 (ja) * 2001-08-24 2012-11-14 ルネサスエレクトロニクス株式会社 半導体装置
US6780776B1 (en) * 2001-12-20 2004-08-24 Advanced Micro Devices, Inc. Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
KR100500439B1 (ko) * 2002-08-14 2005-07-12 삼성전자주식회사 게이트 스페이서가 포지티브 슬로프를 갖는 반도체 장치의 제조방법
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
US6706605B1 (en) * 2003-03-31 2004-03-16 Texas Instruments Incorporated Transistor formed from stacked disposable sidewall spacer
US6913980B2 (en) * 2003-06-30 2005-07-05 Texas Instruments Incorporated Process method of source drain spacer engineering to improve transistor capacitance
US6989567B2 (en) * 2003-10-03 2006-01-24 Infineon Technologies North America Corp. LDMOS transistor
EP1524684B1 (de) * 2003-10-17 2010-01-13 Imec Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen
KR100552808B1 (ko) * 2003-12-24 2006-02-20 동부아남반도체 주식회사 확산 소스/드레인 구조를 갖는 반도체 소자 및 그 제조 방법
KR100562303B1 (ko) * 2003-12-27 2006-03-22 동부아남반도체 주식회사 낮은 접합 커패시턴스를 갖는 모스 트랜지스터 및 그 제조방법
US7161203B2 (en) 2004-06-04 2007-01-09 Micron Technology, Inc. Gated field effect device comprising gate dielectric having different K regions
JP2006173438A (ja) * 2004-12-17 2006-06-29 Yamaha Corp Ｍｏｓ型半導体装置の製法
TW200627643A (en) * 2005-01-19 2006-08-01 Quanta Display Inc A method for manufacturing a thin film transistor
KR100669858B1 (ko) * 2005-05-13 2007-01-16 삼성전자주식회사 고전압 반도체 장치 및 그 제조 방법
JP2007214503A (ja) * 2006-02-13 2007-08-23 Yamaha Corp 半導体装置の製造方法
JP5343320B2 (ja) * 2007-03-02 2013-11-13 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2010029681A1 (ja) * 2008-09-10 2010-03-18 パナソニック株式会社 半導体装置及びその製造方法
CN102800593B (zh) * 2011-05-25 2016-03-16 中芯国际集成电路制造(上海)有限公司 晶体管形成方法
CN104078360B (zh) 2013-03-28 2016-11-23 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
KR102489949B1 (ko) 2016-12-13 2023-01-17 삼성전자주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356623A (en) 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
JPS5833870A (ja) * 1981-08-24 1983-02-28 Hitachi Ltd 半導体装置
DE3581797D1 (de) * 1984-12-27 1991-03-28 Toshiba Kawasaki Kk Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung.
JPS61191070A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置の製造方法
US4746624A (en) * 1986-10-31 1988-05-24 Hewlett-Packard Company Method for making an LDD MOSFET with a shifted buried layer and a blocking region
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte
JPH01173756A (ja) * 1987-12-28 1989-07-10 Toshiba Corp 半導体装置の製造方法
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
JPH0666329B2 (ja) * 1988-06-30 1994-08-24 株式会社東芝 半導体装置の製造方法
US4906589A (en) * 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
US5032530A (en) * 1989-10-27 1991-07-16 Micron Technology, Inc. Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
FR2654257A1 (fr) * 1989-11-03 1991-05-10 Philips Nv Procede pour fabriquer un dispositif a transistors mis ayant une grille debordant sur les portions des regions de source et de drain faiblement dopees.
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
US5091763A (en) * 1990-12-19 1992-02-25 Intel Corporation Self-aligned overlap MOSFET and method of fabrication

Also Published As

Publication number Publication date
US5422506A (en) 1995-06-06
EP0507567B1 (de) 1997-07-30
EP0507567A2 (de) 1992-10-07
US5171700A (en) 1992-12-15
EP0507567A3 (en) 1993-04-21
DE69221188D1 (de) 1997-09-04
JPH05102185A (ja) 1993-04-23

Similar Documents

Publication Publication Date Title
DE69221188T2 (de) Feldeffekttransistorstruktur und Verfahren zur Herstellung
DE69224310T2 (de) Gatestruktur einer Feldeffektanordnung und Verfahren zur Herstellung
DE69218747D1 (de) Lateraler zweifach diffundierter Fieldeffekttransistor mit einem isolierten Gate und Verfahren zur Herstellung
DE69413860D1 (de) Transistoren und Verfahren zur Herstellung
DE69316810D1 (de) SiGe-SOI-MOSFET und Verfahren zur Herstellung
DE69124009T2 (de) Dünnfilmtransistor und Verfahren zur Herstellung
DE69212534D1 (de) Silicongummi-Partikel und Verfahren zur Herstellung
DE69116934D1 (de) Schiffsrumpf und Verfahren zur Herstellung
DE69328985T2 (de) Gate-gesteuerte Diode und Verfahren zur Herstellung derselben
DE69213608T2 (de) Verbundwalze und Verfahren zur Herstellung derselben
DE69120689T2 (de) Feldeffekttransistor mit vertikaler Struktur und Verfahren zur Herstellung
DE69637746D1 (de) Transistor und verfahren zur herstellung
DE69227722D1 (de) Drehender Dichtungselement und Verfahren zur Herstellung
DE69202634T2 (de) Feldemissionsvorrichtung und Verfahren zur Herstellung.
DE69434736D1 (de) Isolationsstruktur und Verfahren zur Herstellung
DE69218501T2 (de) Dünnfilm-Transistoren und Verfahren zur Herstellung
DE69525316T2 (de) Bipolartransistor und Verfahren zur Herstellung desselben
DE69314282D1 (de) Dünnfilmtransistor und Verfahren zur seiner Herstellung
DE69231272D1 (de) Schottky-Dioden-Struktur und Verfahren zur Herstellung
DE69219197D1 (de) Zusammensetzung zur Schmerzlinderung und Verfahren zur Herstellung
DE69128829D1 (de) Feldeffekttransistor und Verfahren zur Herstellung
DE69533996D1 (de) Thyristor und Verfahren zur Herstellung
DE69129453T2 (de) MOSFET-Kanalstruktur und Verfahren zur Herstellung
DE69120836D1 (de) Feldeffekttransistor mit vertikaler Struktur und Verfahren zur Herstellung
DE69220284T2 (de) Magnetkopf und Verfahren zur Herstellung desselben

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee