DE3782279T2 - Elektrisch veraenderbare, nichtfluechtige speicheranordnung vom schwebenden gate-typ, mit geringerer tunneleffektflaeche und herstellung derselben. - Google Patents

Elektrisch veraenderbare, nichtfluechtige speicheranordnung vom schwebenden gate-typ, mit geringerer tunneleffektflaeche und herstellung derselben.

Info

Publication number
DE3782279T2
DE3782279T2 DE8787830233T DE3782279T DE3782279T2 DE 3782279 T2 DE3782279 T2 DE 3782279T2 DE 8787830233 T DE8787830233 T DE 8787830233T DE 3782279 T DE3782279 T DE 3782279T DE 3782279 T2 DE3782279 T2 DE 3782279T2
Authority
DE
Germany
Prior art keywords
manufacture
floating gate
volatile storage
gate type
storage arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787830233T
Other languages
English (en)
Other versions
DE3782279D1 (de
Inventor
Giuseppe Corda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE3782279D1 publication Critical patent/DE3782279D1/de
Application granted granted Critical
Publication of DE3782279T2 publication Critical patent/DE3782279T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/109—Memory devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE8787830233T 1986-06-27 1987-06-22 Elektrisch veraenderbare, nichtfluechtige speicheranordnung vom schwebenden gate-typ, mit geringerer tunneleffektflaeche und herstellung derselben. Expired - Fee Related DE3782279T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT83629/86A IT1191566B (it) 1986-06-27 1986-06-27 Dispositivo di memoria non labile a semiconduttore del tipo a porta non connessa (floating gate) alterabile elettricamente con area di tunnel ridotta e procedimento di fabbricazione

Publications (2)

Publication Number Publication Date
DE3782279D1 DE3782279D1 (de) 1992-11-26
DE3782279T2 true DE3782279T2 (de) 1993-05-19

Family

ID=11323384

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787830233T Expired - Fee Related DE3782279T2 (de) 1986-06-27 1987-06-22 Elektrisch veraenderbare, nichtfluechtige speicheranordnung vom schwebenden gate-typ, mit geringerer tunneleffektflaeche und herstellung derselben.

Country Status (5)

Country Link
US (2) US4931847A (de)
EP (1) EP0252027B1 (de)
JP (1) JPH0824148B2 (de)
DE (1) DE3782279T2 (de)
IT (1) IT1191566B (de)

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US5019879A (en) * 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
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US6525371B2 (en) 1999-09-22 2003-02-25 International Business Machines Corporation Self-aligned non-volatile random access memory cell and process to make the same
JP2001148428A (ja) * 1999-11-18 2001-05-29 Toshiba Microelectronics Corp 半導体装置
JP2001196476A (ja) * 2000-01-07 2001-07-19 Toshiba Corp 半導体装置及びその製造方法
US6627946B2 (en) 2000-09-20 2003-09-30 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with control gates protruding portions
US6727545B2 (en) 2000-09-20 2004-04-27 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling
US6868015B2 (en) 2000-09-20 2005-03-15 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with control gate spacer portions
JP2002100688A (ja) 2000-09-22 2002-04-05 Oki Electric Ind Co Ltd 不揮発性半導体メモリの製造方法
US6563167B2 (en) 2001-01-05 2003-05-13 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges
US6627942B2 (en) 2001-03-29 2003-09-30 Silicon Storage Technology, Inc Self-aligned floating gate poly for a flash E2PROM cell
US6967372B2 (en) 2001-04-10 2005-11-22 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with vertical control gate sidewalls and insulation spacers
US6743674B2 (en) * 2001-09-18 2004-06-01 Silicon Storage Technology, Inc. Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby
US6917069B2 (en) 2001-10-17 2005-07-12 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
US6952033B2 (en) 2002-03-20 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
US6566706B1 (en) 2001-10-31 2003-05-20 Silicon Storage Technology, Inc. Semiconductor array of floating gate memory cells and strap regions
US6541324B1 (en) 2001-11-02 2003-04-01 Silicon Storage Technology, Inc. Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region
US20030102504A1 (en) * 2001-12-05 2003-06-05 Geeng-Chuan Chern Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric
US6756633B2 (en) * 2001-12-27 2004-06-29 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges
US6861698B2 (en) * 2002-01-24 2005-03-01 Silicon Storage Technology, Inc. Array of floating gate memory cells having strap regions and a peripheral logic device region
US6878591B2 (en) * 2002-02-07 2005-04-12 Silicon Storage Technology, Inc. Self aligned method of forming non-volatile memory cells with flat word line
US7411246B2 (en) * 2002-04-01 2008-08-12 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
US6891220B2 (en) * 2002-04-05 2005-05-10 Silicon Storage Technology, Inc. Method of programming electrons onto a floating gate of a non-volatile memory cell
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US6706592B2 (en) * 2002-05-14 2004-03-16 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor array of non-volatile memory cells
US6873006B2 (en) * 2003-03-21 2005-03-29 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region
US6958273B2 (en) * 2003-03-21 2005-10-25 Silicon Storage Technology, Inc. Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby
US6919242B2 (en) * 2003-04-25 2005-07-19 Atmel Corporation Mirror image memory cell transistor pairs featuring poly floating spacers
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
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US7098106B2 (en) * 2004-07-01 2006-08-29 Atmel Corporation Method of making mirror image memory cell transistor pairs featuring poly floating spacers
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US7641226B2 (en) * 2006-11-01 2010-01-05 Autoliv Development Ab Side airbag module with an internal guide fin
US7915664B2 (en) * 2008-04-17 2011-03-29 Sandisk Corporation Non-volatile memory with sidewall channels and raised source/drain regions
US8148768B2 (en) * 2008-11-26 2012-04-03 Silicon Storage Technology, Inc. Non-volatile memory cell with self aligned floating and erase gates, and method of making same
CN111223868A (zh) * 2018-11-27 2020-06-02 钰成投资股份有限公司 半导体非挥发性存储元件结构

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Also Published As

Publication number Publication date
EP0252027A2 (de) 1988-01-07
EP0252027A3 (en) 1988-07-20
JPS639981A (ja) 1988-01-16
US5081057A (en) 1992-01-14
EP0252027B1 (de) 1992-10-21
DE3782279D1 (de) 1992-11-26
US4931847A (en) 1990-06-05
IT1191566B (it) 1988-03-23
JPH0824148B2 (ja) 1996-03-06
IT8683629A0 (it) 1986-06-27

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee