DE3585015D1 - Bipolarer transistor-direktzugriffsspeicher mit redundanzkonfiguration. - Google Patents

Bipolarer transistor-direktzugriffsspeicher mit redundanzkonfiguration.

Info

Publication number
DE3585015D1
DE3585015D1 DE8585307560T DE3585015T DE3585015D1 DE 3585015 D1 DE3585015 D1 DE 3585015D1 DE 8585307560 T DE8585307560 T DE 8585307560T DE 3585015 T DE3585015 T DE 3585015T DE 3585015 D1 DE3585015 D1 DE 3585015D1
Authority
DE
Germany
Prior art keywords
access memory
bipolar transistor
direct access
redundancy configuration
transistor direct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585307560T
Other languages
English (en)
Inventor
Yoshinori Okajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59218707A external-priority patent/JPS61100000A/ja
Priority claimed from JP59243340A external-priority patent/JPS61123099A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3585015D1 publication Critical patent/DE3585015D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
DE8585307560T 1984-10-19 1985-10-18 Bipolarer transistor-direktzugriffsspeicher mit redundanzkonfiguration. Expired - Fee Related DE3585015D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59218707A JPS61100000A (ja) 1984-10-19 1984-10-19 情報記憶装置
JP59243340A JPS61123099A (ja) 1984-11-20 1984-11-20 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3585015D1 true DE3585015D1 (de) 1992-02-06

Family

ID=26522707

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585307560T Expired - Fee Related DE3585015D1 (de) 1984-10-19 1985-10-18 Bipolarer transistor-direktzugriffsspeicher mit redundanzkonfiguration.

Country Status (4)

Country Link
US (1) US4744060A (de)
EP (1) EP0178948B1 (de)
KR (1) KR900008659B1 (de)
DE (1) DE3585015D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371500A (ja) * 1989-08-11 1991-03-27 Sony Corp 半導体メモリ
JP2547451B2 (ja) * 1989-09-18 1996-10-23 富士通株式会社 半導体記憶装置
JPH05166396A (ja) * 1991-12-12 1993-07-02 Mitsubishi Electric Corp 半導体メモリ装置
JP2741824B2 (ja) * 1992-10-14 1998-04-22 三菱電機株式会社 半導体記憶装置
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
FR2716743B1 (fr) * 1994-02-28 1996-09-27 Sgs Thomson Microelectronics Circuit de redondance de mémoire.
JP2914171B2 (ja) * 1994-04-25 1999-06-28 松下電器産業株式会社 半導体メモリ装置およびその駆動方法
US7174477B2 (en) * 2003-02-04 2007-02-06 Micron Technology, Inc. ROM redundancy in ROM embedded DRAM

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1963895C3 (de) * 1969-06-21 1973-11-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Datenspeicher und Datenspeicher anste'uerschaltung
JPS5928560Y2 (ja) * 1979-11-13 1984-08-17 富士通株式会社 冗長ビットを有する記憶装置
JPS5685934A (en) * 1979-12-14 1981-07-13 Nippon Telegr & Teleph Corp <Ntt> Control signal generating circuit
US4462091A (en) * 1982-02-26 1984-07-24 International Business Machines Corporation Word group redundancy scheme
JPS595497A (ja) * 1982-07-02 1984-01-12 Hitachi Ltd 半導体ｒｏｍ

Also Published As

Publication number Publication date
US4744060A (en) 1988-05-10
EP0178948A3 (en) 1988-01-13
KR900008659B1 (ko) 1990-11-26
KR860003665A (ko) 1986-05-28
EP0178948A2 (de) 1986-04-23
EP0178948B1 (de) 1991-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee