DE3680371D1 - Speicher mit auswaehlbarer wortlaenge. - Google Patents

Speicher mit auswaehlbarer wortlaenge.

Info

Publication number
DE3680371D1
DE3680371D1 DE8686104924T DE3680371T DE3680371D1 DE 3680371 D1 DE3680371 D1 DE 3680371D1 DE 8686104924 T DE8686104924 T DE 8686104924T DE 3680371 T DE3680371 T DE 3680371T DE 3680371 D1 DE3680371 D1 DE 3680371D1
Authority
DE
Germany
Prior art keywords
storage
word length
selectable word
selectable
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686104924T
Other languages
English (en)
Inventor
Shinobu C O Nec Corpora Miyata
Takashige C Nec Corpo Kinouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3680371D1 publication Critical patent/DE3680371D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
DE8686104924T 1985-04-10 1986-04-10 Speicher mit auswaehlbarer wortlaenge. Expired - Lifetime DE3680371D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7573485 1985-04-10

Publications (1)

Publication Number Publication Date
DE3680371D1 true DE3680371D1 (de) 1991-08-29

Family

ID=13584796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686104924T Expired - Lifetime DE3680371D1 (de) 1985-04-10 1986-04-10 Speicher mit auswaehlbarer wortlaenge.

Country Status (4)

Country Link
US (1) US4706219A (de)
EP (1) EP0198429B1 (de)
JP (1) JPH079976B2 (de)
DE (1) DE3680371D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736269B2 (ja) * 1985-08-30 1995-04-19 株式会社日立製作所 半導体記憶装置
US4819212A (en) * 1986-05-31 1989-04-04 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with readout test circuitry
JPS635444A (ja) * 1986-06-25 1988-01-11 Hitachi Ltd マイクロプロセツサ
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
DE3884492T2 (de) * 1987-07-15 1994-02-17 Hitachi Ltd Integrierte Halbleiterschaltungsanordnung.
US5257234A (en) * 1987-07-15 1993-10-26 Hitachi, Ltd. Semiconductor integrated circuit device
JPH0697560B2 (ja) * 1987-11-19 1994-11-30 三菱電機株式会社 半導体記憶装置
JP2600304B2 (ja) * 1988-06-30 1997-04-16 三菱電機株式会社 半導体記憶装置とこれを用いたデータパス
JPH02168496A (ja) * 1988-09-14 1990-06-28 Kawasaki Steel Corp 半導体メモリ回路
JP2871975B2 (ja) * 1992-09-29 1999-03-17 日本電気アイシーマイコンシステム株式会社 半導体メモリ装置
JPH0855471A (ja) * 1994-08-12 1996-02-27 Nec Corp 同期型半導体記憶装置
US5689462A (en) * 1995-12-22 1997-11-18 Townsend And Townsend And Crew, Llp Parallel output buffers in memory circuits
US5900021A (en) * 1997-04-04 1999-05-04 United Memories, Inc. Pad input select circuit for use with bond options
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
DE10339343A1 (de) * 2003-08-25 2005-05-04 Zentr Mikroelekt Dresden Gmbh Verfahren und Anordnung zur Herstellung eines Speicher-Chips mit verschiedenen Datenbitbreiten
KR100532471B1 (ko) * 2003-09-26 2005-12-01 삼성전자주식회사 입출력 데이터 위스 조절이 가능한 메모리 장치 및 그위스 조절 방법
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595987B2 (ja) * 1976-11-05 1984-02-08 株式会社日立製作所 半導体メモリ素子
JPS54128226A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Random access memory
JPS55150179A (en) * 1979-05-04 1980-11-21 Fujitsu Ltd Semiconductor memory unit
JPS57127989A (en) * 1981-02-02 1982-08-09 Hitachi Ltd Mos static type ram
JPS5860480A (ja) * 1981-10-06 1983-04-09 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ
JPH0652784B2 (ja) * 1984-12-07 1994-07-06 富士通株式会社 ゲートアレイ集積回路装置及びその製造方法

Also Published As

Publication number Publication date
US4706219A (en) 1987-11-10
EP0198429A3 (en) 1988-08-17
EP0198429A2 (de) 1986-10-22
JPH079976B2 (ja) 1995-02-01
JPS6242444A (ja) 1987-02-24
EP0198429B1 (de) 1991-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP