DE3582999D1 - Speicheranordnung mit abschaltungssteuerung. - Google Patents

Speicheranordnung mit abschaltungssteuerung.

Info

Publication number
DE3582999D1
DE3582999D1 DE8585113713T DE3582999T DE3582999D1 DE 3582999 D1 DE3582999 D1 DE 3582999D1 DE 8585113713 T DE8585113713 T DE 8585113713T DE 3582999 T DE3582999 T DE 3582999T DE 3582999 D1 DE3582999 D1 DE 3582999D1
Authority
DE
Germany
Prior art keywords
shut
control
storage arrangement
arrangement
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585113713T
Other languages
English (en)
Inventor
Yasuo Akatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3582999D1 publication Critical patent/DE3582999D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE8585113713T 1984-10-29 1985-10-29 Speicheranordnung mit abschaltungssteuerung. Expired - Fee Related DE3582999D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59227303A JPS61105795A (ja) 1984-10-29 1984-10-29 メモリ回路

Publications (1)

Publication Number Publication Date
DE3582999D1 true DE3582999D1 (de) 1991-07-04

Family

ID=16858697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585113713T Expired - Fee Related DE3582999D1 (de) 1984-10-29 1985-10-29 Speicheranordnung mit abschaltungssteuerung.

Country Status (4)

Country Link
US (1) US4718043A (de)
EP (1) EP0180895B1 (de)
JP (1) JPS61105795A (de)
DE (1) DE3582999D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
JPH0197016A (ja) * 1987-10-09 1989-04-14 Fujitsu Ltd 半導体集積回路装置
JP2679093B2 (ja) * 1988-03-26 1997-11-19 セイコーエプソン株式会社 Ｉｃメモリーカード
US5164652A (en) * 1989-04-21 1992-11-17 Motorola, Inc. Method and apparatus for determining battery type and modifying operating characteristics
US5197034A (en) * 1991-05-10 1993-03-23 Intel Corporation Floating gate non-volatile memory with deep power down and write lock-out
JP3058986B2 (ja) * 1992-04-02 2000-07-04 ダイヤセミコンシステムズ株式会社 コンピュータシステムの節電制御装置
US5301165A (en) * 1992-10-28 1994-04-05 International Business Machines Corporation Chip select speedup circuit for a memory
US6384623B1 (en) * 1993-01-07 2002-05-07 Hitachi, Ltd. Semiconductor integrated circuits with power reduction mechanism
US7388400B2 (en) * 1993-01-07 2008-06-17 Elpida Memory, Inc. Semiconductor integrated circuits with power reduction mechanism
US5406554A (en) * 1993-10-05 1995-04-11 Music Semiconductors, Corp. Synchronous FIFO having an alterable buffer store
JP2838967B2 (ja) * 1993-12-17 1998-12-16 日本電気株式会社 同期型半導体装置用パワーカット回路
US5710933A (en) * 1995-03-31 1998-01-20 International Business Machines Corporation System resource enable apparatus
US5668769A (en) * 1995-11-21 1997-09-16 Texas Instruments Incorporated Memory device performance by delayed power-down
KR100269313B1 (ko) * 1997-11-07 2000-12-01 윤종용 대기시전류소모가적은반도체메모리장치
KR100326268B1 (ko) 1998-10-28 2002-05-09 박종섭 디코딩시의동작마진확보를위한디코딩장치및그방법
JP2001338489A (ja) * 2000-05-24 2001-12-07 Mitsubishi Electric Corp 半導体装置
JP4717983B2 (ja) * 2000-06-14 2011-07-06 株式会社日立製作所 省消費電力型メモリモジュール及び計算機システム
KR100426443B1 (ko) * 2002-06-29 2004-04-13 주식회사 하이닉스반도체 딥 파워다운 제어 회로
JP3724464B2 (ja) * 2002-08-19 2005-12-07 株式会社デンソー 半導体圧力センサ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087704A (en) * 1974-11-04 1978-05-02 Intel Corporation Sequential timing circuitry for a semiconductor memory
US4337525A (en) * 1979-04-17 1982-06-29 Nippon Electric Co., Ltd. Asynchronous circuit responsive to changes in logic level
JPS5712478A (en) * 1980-06-23 1982-01-22 Hitachi Ltd Static type mis ram
WO1982004345A1 (en) * 1981-05-27 1982-12-09 Aswell Cecil James Power supply control for integrated circuit
JPS5891591A (ja) * 1981-11-27 1983-05-31 Toshiba Corp 半導体メモリのパワ−セ−ブ方式
JPS59135696A (ja) * 1983-01-24 1984-08-03 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0180895B1 (de) 1991-05-29
EP0180895A3 (en) 1988-02-10
EP0180895A2 (de) 1986-05-14
US4718043A (en) 1988-01-05
JPS61105795A (ja) 1986-05-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee