DE3585517D1 - Mikroprozessor mit variabler speicherkapazitaet. - Google Patents

Mikroprozessor mit variabler speicherkapazitaet.

Info

Publication number
DE3585517D1
DE3585517D1 DE8585115754T DE3585517T DE3585517D1 DE 3585517 D1 DE3585517 D1 DE 3585517D1 DE 8585115754 T DE8585115754 T DE 8585115754T DE 3585517 T DE3585517 T DE 3585517T DE 3585517 D1 DE3585517 D1 DE 3585517D1
Authority
DE
Germany
Prior art keywords
microprocessor
storage capacity
variable storage
variable
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585115754T
Other languages
English (en)
Inventor
Akio Miyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3585517D1 publication Critical patent/DE3585517D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
DE8585115754T 1984-12-11 1985-12-11 Mikroprozessor mit variabler speicherkapazitaet. Expired - Lifetime DE3585517D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59261377A JPS61139866A (ja) 1984-12-11 1984-12-11 マイクロプロセツサ

Publications (1)

Publication Number Publication Date
DE3585517D1 true DE3585517D1 (de) 1992-04-09

Family

ID=17360997

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585115754T Expired - Lifetime DE3585517D1 (de) 1984-12-11 1985-12-11 Mikroprozessor mit variabler speicherkapazitaet.

Country Status (4)

Country Link
US (1) US4766538A (de)
EP (1) EP0187293B1 (de)
JP (1) JPS61139866A (de)
DE (1) DE3585517D1 (de)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226561A (ja) * 1985-07-26 1987-02-04 Toshiba Corp パ−ソナルコンピユ−タ
GB2211326B (en) * 1987-10-16 1991-12-11 Hitachi Ltd Address bus control apparatus
US5214767A (en) * 1989-02-07 1993-05-25 Compaq Computer Corp. Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes
US5168562A (en) * 1989-02-21 1992-12-01 Compaq Computer Corporation Method and apparatus for determining the allowable data path width of a device in a computer system to avoid interference with other devices
US5163145A (en) * 1989-04-25 1992-11-10 Dell Usa L.P. Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference
JP2504206B2 (ja) * 1989-07-27 1996-06-05 三菱電機株式会社 バスコントロ―ラ
JPH0398145A (ja) * 1989-09-11 1991-04-23 Hitachi Ltd マイクロプロセッサ
EP0860780A3 (de) * 1990-03-02 1999-06-30 Fujitsu Limited Bussteuerungssystem in einem Multiprozessorsystem
KR0181471B1 (ko) * 1990-07-27 1999-05-15 윌리암 피.브레이든 컴퓨터 데이타 경로배정 시스템
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
US5887196A (en) * 1991-12-30 1999-03-23 Apple Computer, Inc. System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer
JPH05257851A (ja) * 1991-12-30 1993-10-08 Apple Computer Inc データの転送の順序を制御させる装置
US5410677A (en) * 1991-12-30 1995-04-25 Apple Computer, Inc. Apparatus for translating data formats starting at an arbitrary byte position
US5640599A (en) * 1991-12-30 1997-06-17 Apple Computer, Inc. Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed
US5848297A (en) * 1991-12-30 1998-12-08 Apple Computer, Inc. Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect
JPH07504773A (ja) * 1992-03-18 1995-05-25 セイコーエプソン株式会社 マルチ幅のメモリ・サブシステムをサポートするためのシステム並びに方法
EP0597601A1 (de) * 1992-11-13 1994-05-18 National Semiconductor Corporation Speicherbusschnittstelle mit erwägter Breiteninstellung
JP3483594B2 (ja) * 1993-07-20 2004-01-06 富士通株式会社 半導体装置
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
US5649127A (en) * 1994-05-04 1997-07-15 Samsung Semiconductor, Inc. Method and apparatus for packing digital data
US6263321B1 (en) * 1994-07-29 2001-07-17 Economic Inventions, Llc Apparatus and process for calculating an option
US5745606A (en) * 1995-10-11 1998-04-28 Yoshimichi; Kanda Method and system for storing information in compressed block data
US5918027A (en) * 1995-12-15 1999-06-29 Nec Corporation Data processor having bus controller
US5812798A (en) * 1996-01-26 1998-09-22 Motorola, Inc. Data processing system for accessing an external device and method therefore
JPH09204243A (ja) * 1996-01-29 1997-08-05 Fujitsu Ltd データ転送方法
US5916312A (en) * 1997-05-06 1999-06-29 Sony Corporation ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members
JPH1124989A (ja) * 1997-07-07 1999-01-29 Nec Corp 語長可変メモリアクセス方式
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
US6889304B2 (en) * 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
JP2003208399A (ja) * 2002-01-15 2003-07-25 Hitachi Ltd データ処理装置
US6904486B2 (en) 2002-05-23 2005-06-07 Seiko Epson Corporation 32 bit generic bus interface using read/write byte enables
US6886067B2 (en) * 2002-05-23 2005-04-26 Seiko Epson Corporation 32 Bit generic asynchronous bus interface using read/write strobe byte enables
JP2004087027A (ja) * 2002-08-28 2004-03-18 Sanyo Electric Co Ltd アクセス回路
CA2554829C (en) * 2004-02-05 2009-11-03 Research In Motion Limited System and method for detecting the width of a data bus
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7254075B2 (en) * 2004-09-30 2007-08-07 Rambus Inc. Integrated circuit memory system having dynamic memory bank count and page size
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20060184726A1 (en) * 2005-02-11 2006-08-17 Nokia Corporation Flexible access and control of Dynamic Random Access Memory
CN1870873A (zh) * 2005-05-28 2006-11-29 深圳富泰宏精密工业有限公司 铰链装置及应用该铰链装置的便携式电子装置
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5597120B2 (ja) * 2010-12-13 2014-10-01 株式会社ザクティ メモリアクセス装置
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2021823B (en) * 1978-05-30 1983-04-27 Intel Corp Data transfer system
DE3177233D1 (de) * 1980-03-19 1990-12-20 Toshiba Kawasaki Kk Datenverarbeitungssystem.
US4519028A (en) * 1981-02-17 1985-05-21 Digital Equipment Corporation CPU with multi-stage mode register for defining CPU operating environment including charging its communications protocol
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
US4663729A (en) * 1984-06-01 1987-05-05 International Business Machines Corp. Display architecture having variable data width

Also Published As

Publication number Publication date
US4766538A (en) 1988-08-23
EP0187293B1 (de) 1992-03-04
EP0187293A3 (en) 1988-06-15
EP0187293A2 (de) 1986-07-16
JPS61139866A (ja) 1986-06-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee