DE3576245D1 - Verfahren zur herstellung eines nichtfluechtigen halbleiter-eeprom-elementes. - Google Patents

Verfahren zur herstellung eines nichtfluechtigen halbleiter-eeprom-elementes.

Info

Publication number
DE3576245D1
DE3576245D1 DE8585106028T DE3576245T DE3576245D1 DE 3576245 D1 DE3576245 D1 DE 3576245D1 DE 8585106028 T DE8585106028 T DE 8585106028T DE 3576245 T DE3576245 T DE 3576245T DE 3576245 D1 DE3576245 D1 DE 3576245D1
Authority
DE
Germany
Prior art keywords
producing
volatile semiconductor
eeprom element
semiconductor eeprom
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585106028T
Other languages
English (en)
Inventor
Naohiro C O Patent D Matsukawa
Sigeru C O Patent Divis Morita
Hiroshi C O Patent Divi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59099262A external-priority patent/JPS60244073A/ja
Priority claimed from JP59177436A external-priority patent/JPS6155965A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3576245D1 publication Critical patent/DE3576245D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Non-Volatile Memory (AREA)
DE8585106028T 1984-05-17 1985-05-15 Verfahren zur herstellung eines nichtfluechtigen halbleiter-eeprom-elementes. Expired - Lifetime DE3576245D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59099262A JPS60244073A (ja) 1984-05-17 1984-05-17 不揮発性半導体記憶装置の製造方法
JP59177436A JPS6155965A (ja) 1984-08-28 1984-08-28 不揮発性半導体記憶装置の製造方法

Publications (1)

Publication Number Publication Date
DE3576245D1 true DE3576245D1 (de) 1990-04-05

Family

ID=26440414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585106028T Expired - Lifetime DE3576245D1 (de) 1984-05-17 1985-05-15 Verfahren zur herstellung eines nichtfluechtigen halbleiter-eeprom-elementes.

Country Status (3)

Country Link
US (1) US4642881A (de)
EP (1) EP0164605B1 (de)
DE (1) DE3576245D1 (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750693B2 (ja) * 1985-12-02 1995-05-31 日本テキサス・インスツルメンツ株式会社 酸化シリコン膜の製造方法
US5189497A (en) * 1986-05-26 1993-02-23 Hitachi, Ltd. Semiconductor memory device
JP2555027B2 (ja) * 1986-05-26 1996-11-20 株式会社日立製作所 半導体記憶装置
JP3059442B2 (ja) 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
IT1191566B (it) * 1986-06-27 1988-03-23 Sgs Microelettronica Spa Dispositivo di memoria non labile a semiconduttore del tipo a porta non connessa (floating gate) alterabile elettricamente con area di tunnel ridotta e procedimento di fabbricazione
US5156990A (en) * 1986-07-23 1992-10-20 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
JP2633541B2 (ja) * 1987-01-07 1997-07-23 株式会社東芝 半導体メモリ装置の製造方法
EP0298430A3 (de) * 1987-07-08 1990-05-16 Hitachi, Ltd. Halbleiter Anordnung mit schwimmender Gate
JP2672537B2 (ja) * 1987-12-21 1997-11-05 株式会社東芝 不揮発性半導体装置の製造方法
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US5086008A (en) * 1988-02-29 1992-02-04 Sgs-Thomson Microelectronics S.R.L. Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology
US5028553A (en) * 1988-06-03 1991-07-02 Texas Instruments Incorporated Method of making fast, trench isolated, planar flash EEPROMS with silicided bitlines
US5237193A (en) * 1988-06-24 1993-08-17 Siliconix Incorporated Lightly doped drain MOSFET with reduced on-resistance
EP0366423B1 (de) * 1988-10-25 1994-05-25 Matsushita Electronics Corporation Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung
US5081054A (en) * 1989-04-03 1992-01-14 Atmel Corporation Fabrication process for programmable and erasable MOS memory device
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5111270A (en) * 1990-02-22 1992-05-05 Intel Corporation Three-dimensional contactless non-volatile memory cell
US5225361A (en) * 1990-03-08 1993-07-06 Matshshita Electronics Coropration Non-volatile semiconductor memory device and a method for fabricating the same
JPH0770629B2 (ja) * 1990-03-20 1995-07-31 株式会社東芝 不揮発性半導体記憶装置の製造方法
JP2519608B2 (ja) * 1990-04-16 1996-07-31 三菱電機株式会社 半導体装置およびその製造方法
US5411904A (en) * 1990-11-19 1995-05-02 Sharp Kabushiki Kaisha Process for fabricating nonvolatile random access memory having a tunnel oxide film
US5094968A (en) * 1990-11-21 1992-03-10 Atmel Corporation Fabricating a narrow width EEPROM with single diffusion electrode formation
US5086325A (en) * 1990-11-21 1992-02-04 Atmel Corporation Narrow width EEPROM with single diffusion electrode formation
US5270240A (en) * 1991-07-10 1993-12-14 Micron Semiconductor, Inc. Four poly EPROM process and structure comprising a conductive source line structure and self-aligned polycrystalline silicon digit lines
US5198381A (en) * 1991-09-12 1993-03-30 Vlsi Technology, Inc. Method of making an E2 PROM cell with improved tunneling properties having two implant stages
US5190887A (en) * 1991-12-30 1993-03-02 Intel Corporation Method of making electrically erasable and electrically programmable memory cell with extended cycling endurance
JP3271105B2 (ja) * 1993-10-28 2002-04-02 ソニー株式会社 半導体装置及びその形成方法
JP3541958B2 (ja) * 1993-12-16 2004-07-14 株式会社東芝 不揮発性半導体記憶装置
US5404037A (en) * 1994-03-17 1995-04-04 National Semiconductor Corporation EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region
US5648669A (en) * 1995-05-26 1997-07-15 Cypress Semiconductor High speed flash memory cell structure and method
US5844271A (en) * 1995-08-21 1998-12-01 Cypress Semiconductor Corp. Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate
EP0779646A1 (de) * 1995-12-14 1997-06-18 STMicroelectronics S.r.l. Verfahren zur Herstellung von EEPROM-Speicheranordnungen und so hergestellte EEPROM-Speicheranordnungen
KR0180310B1 (ko) * 1995-12-28 1999-03-20 김광호 상보형 모스 트랜지스터 및 그 제조방법
DE19620032C2 (de) * 1996-05-17 1998-07-09 Siemens Ag Halbleiterbauelement mit Kompensationsimplantation und Herstellverfahren
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US5897354A (en) * 1996-12-17 1999-04-27 Cypress Semiconductor Corporation Method of forming a non-volatile memory device with ramped tunnel dielectric layer
US6127222A (en) * 1997-12-16 2000-10-03 Advanced Micro Devices, Inc. Non-self-aligned side channel implants for flash memory cells
US6017786A (en) * 1997-12-17 2000-01-25 Advanced Micro Devices, Inc. Method for forming a low barrier height oxide layer on a silicon substrate
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
KR19990060472A (ko) * 1997-12-31 1999-07-26 구본준 반도체소자의 산화막 형성방법
US6268296B1 (en) * 1997-12-31 2001-07-31 Texas Instruments Incorporated Low temperature process for multiple voltage devices
JP4809545B2 (ja) * 2001-05-31 2011-11-09 株式会社半導体エネルギー研究所 半導体不揮発性メモリ及び電子機器
US6551883B1 (en) * 2001-12-27 2003-04-22 Silicon Integrated Systems Corp. MOS device with dual gate insulators and method of forming the same
KR100552839B1 (ko) * 2003-11-05 2006-02-22 동부아남반도체 주식회사 반도체 소자 및 이의 제조 방법
JP2016051812A (ja) * 2014-08-29 2016-04-11 キヤノン株式会社 接合型電界効果トランジスタの製造方法、半導体装置の製造方法、撮像装置の製造方法、接合型電界効果トランジスタ及び撮像装置

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US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
US4149905A (en) * 1977-12-27 1979-04-17 Bell Telephone Laboratories, Incorporated Method of limiting stacking faults in oxidized silicon wafers
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
JPS5519851A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Manufacture of non-volatile memories
US4257056A (en) * 1979-06-27 1981-03-17 National Semiconductor Corporation Electrically erasable read only memory
US4514897A (en) * 1979-09-04 1985-05-07 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US4409723A (en) * 1980-04-07 1983-10-18 Eliyahou Harari Method of forming non-volatile EPROM and EEPROM with increased efficiency
US4519849A (en) * 1980-10-14 1985-05-28 Intel Corporation Method of making EPROM cell with reduced programming voltage
JPS57112078A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of electrically rewritable fixed memory
US4490900A (en) * 1982-01-29 1985-01-01 Seeq Technology, Inc. Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein
JPS59920A (ja) * 1982-06-23 1984-01-06 Fujitsu Ltd 半導体装置の製造方法
JPS5963763A (ja) * 1982-10-05 1984-04-11 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
US4642881A (en) 1987-02-17
EP0164605A2 (de) 1985-12-18
EP0164605B1 (de) 1990-02-28
EP0164605A3 (en) 1987-08-19

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)